PXS20 Product Brief, Rev. 1

Features

Freescale Semiconductor

26

2.5.39

Built-In Self-Test (BIST) Capability

This device includes the following protection against latent faults:

•

Boot-time Memory Built-In Self-Test (MBIST)

•

Boot-time scan-based Logic Built-In Self-Test (LBIST)

•

Run-time ADC Built-In Self-Test (BIST)

•

Run-time Built-In Self Test of LVDs

2.5.40

IEEE 1149.1 JTAG Controller (JTAGC)

The JTAGC block provides the means to test chip functionality and connectivity while remaining

transparent to system logic when not in test mode. All data input to and output from the JTAGC block is

communicated in serial format. The JTAGC block is compliant with the IEEE standard.

The JTAG controller provides the following features:

•

IEEE Test Access Port (TAP) interface with 5 pins:

—TDI

—TMS

—TCK

—TDO

—JCOMP

•

Selectable modes of operation include JTAGC/debug or normal system operation

•

5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:

—BYPASS

—IDCODE

—EXTEST

—SAMPLE

— SAMPLE/PRELOAD

•

3 test data registers: a bypass register, a boundary scan register, and a device identification register.

The size of the boundary scan register is parameterized to support a variety of boundary scan chain

lengths.

•

TAP controller state machine that controls the operation of the data registers, instruction register

and associated circuitry

2.5.41

Nexus Port Controller (NPC)

The NPC module provides real-time development support capabilities for this device in compliance with

the IEEE-ISTO 5001-2008 standard. This development support is supplied for MCUs without requiring

external address and data pins for internal visibility.

The NPC block interfaces to the host processor and internal buses to provide development support as per

the IEEE-ISTO 5001-2008 Class 3+, including selected features from Class 4 standard.