PXS20 Product Brief, Rev. 1

Features

Freescale Semiconductor

12

ECC handling is done on a 32-bit boundary for data and it is extended to the address to have the highest

possible diagnostic coverage including the array internal address decoder.

The SRAM module provides the following features:

•

System SRAM: 128 KB

•

ECC on 32-bit word (syndrome of 7 bits)

— ECC covers SRAM bus address

•

1-bit error correction, 2-bit error detection

•

Wait states:

— 1 wait state at 120 MHz

— 0 wait states at 80 MHz and 60 MHz

2.5.7

Platform Flash Memory Controller

The following list summarizes the key features of the flash memory controller:

•

Single AHB port interface supports a 64-bit data bus. All AHB aligned and unaligned reads within

the 32-bit container are supported. Only aligned word writes are supported.

•

Array interfaces support a 128-bit read data bus and a 64-bit write data bus for each bank.

•

Code flash (bank0) interface provides configurable read buffering and page prefetch support.

— Four page-read buffers (each 128 bits wide) and a prefetch controller support speculative

reading and optimized flash access.

•

Single-cycle read responses (0 AHB data-phase wait states) for hits in the buffers. The buffers

implement a least-recently-used replacement algorithm to maximize performance.

•

Data flash (bank1) interface includes a 128-bit register to temporarily hold a single flash page. This

logic supports single-cycle read responses (0 AHB data-phase wait states) for accesses that hit in

the holding register.

— No prefetch support is provided for this bank.

•

Programmable response for read-while-write sequences including support for stall-while-write,

optional stall notification interrupt, optional flash operation abort , and optional abort notification

interrupt.

•

Separate and independent configurable access timing (on a per bank basis) to support use across a

wide range of platforms and frequencies.

•

Support of address-based read access timing for emulation of other memory types.

•

Support for reporting of single- and multi-bit error events.

•

Typical operating configuration loaded into programming model by system reset.

The platform flash controller is replicated for each processor.

2.5.8

Platform Static RAM Controller (SRAMC)

The SRAMC module is the platform SRAM array controller, with integrated error detection and

correction.