Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

Preview PDF HTML

CY8C54LP Datasheet(PDF) 80 Page - Cypress Semiconductor

Part # CY8C54LP
Description  Programmable System-on-Chip (PSoC짰)
PDF  117 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C54LP Datasheet(HTML) 80 Page - Cypress Semiconductor

Back Button CY8C54LP Datasheet HTML 76Page - Cypress Semiconductor CY8C54LP Datasheet HTML 77Page - Cypress Semiconductor CY8C54LP Datasheet HTML 78Page - Cypress Semiconductor CY8C54LP Datasheet HTML 79Page - Cypress Semiconductor CY8C54LP Datasheet HTML 80Page - Cypress Semiconductor CY8C54LP Datasheet HTML 81Page - Cypress Semiconductor CY8C54LP Datasheet HTML 82Page - Cypress Semiconductor CY8C54LP Datasheet HTML 83Page - Cypress Semiconductor CY8C54LP Datasheet HTML 84Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 80 / 117 page
background image
PRELIMINARY
PSoC® 5LP: CY8C54LP Family
Datasheet
Document Number: 001-84934 Rev. **
Page 80 of 117
11.5.2 Voltage Reference
Figure 11-27. Vref vs Temperature
Figure 11-28. Vref Long-term Drift
11.5.3 SAR ADC
Table 11-20. Voltage Reference Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
VREF
Precision reference voltage
Initial trimming
1.023
(–0.1%)
1.024
1.025
(+0.1%)
V
Temperature drift[35]
–
–
30
ppm/°C
Long term drift
–
100
–
ppm/Khr
Thermal cycling drift (stability)[35]
–100
–
ppm
Table 11-21. SAR ADC DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Resolution
–
–
12
bits
Number of channels – single-ended
–
–
No of
GPIO
Number of channels – differential
Differential pair is formed using a
pair of neighboring GPIO.
––
No of
GPIO/2
Monotonicity[35]
Yes
–
–
Ge
Gain error[36]
External reference
–
–
±0.1
%
VOS
Input offset voltage
–
–
±2
mV
IDD
Current consumption
–
–
1
mA
Input voltage range –
single-ended[35]
VSSA
–VDDA
V
Input voltage range – differential[35]
VSSA
–VDDA
V
PSRR
Power supply rejection ratio[35]
70
–
–
dB
CMRR
Common mode rejection ratio
70
–
–
dB
Notes
35. Based on device characterization (Not production tested).
36. For total analog system Idd < 5 mA, depending on package used. With higher total analog system currents it is recommended that the SAR ADC be used in differential
mode.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com