CY8C54LP datasheet(29/117 Pages) CYPRESS

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PRELIMINARY

PSoC® 5LP: CY8C54LP Family

Datasheet

Document Number: 001-84934 Rev. **

Page 29 of 117

In normal operating mode, the program cannot disable the

digital PRES circuit. The analog regulator can be disabled,

which also disables the analog portion of the PRES. The PRES

circuit is disabled automatically during sleep and hibernate

modes, with one exception: During sleep mode the regulators

are periodically activated (buzzed) to provide supervisory

services and to reduce wakeup time. At these times the PRES

circuit is also buzzed to allow periodic voltage monitoring.

After PRES has been deasserted, at least 10 µs must elapse

before it can be reasserted.

ALVI, DLVI, AHVI - Analog/Digital Low Voltage Interrupt, Analog

High Voltage Interrupt

Interrupt circuits are available to detect when VDDA and

VDDD go outside a voltage range. For AHVI, VDDA is

compared to a fixed trip level. For ALVI and DLVI, VDDA and

VDDD are compared to trip levels that are programmable, as

listed in Table 6-5. ALVI and DLVI can also be configured to

generate a device reset instead of an interrupt.

The monitors are disabled until after IPOR. During sleep mode

these circuits are periodically activated (buzzed). If an interrupt

occurs during buzzing then the system first enters its wakeup

sequence. The interrupt is then recognized and may be

serviced.

The buzz frequency is adjustable, and should be set to be less

than the minimum time that any voltage is expected to be out

of range. For details on how to adjust the buzz frequency, see

the TRM.

6.3.1.2

Other Reset Sources

XRES - External Reset

PSoC 5LP has either a single GPIO pin that is configured as

an external reset or a dedicated XRES pin. Either the

dedicated XRES pin or the GPIO pin, if configured, holds the

part in reset while held active (low). The response to an XRES

is the same as to an IPOR reset.

The external reset is active low. It includes an internal pull-up

resistor. XRES is active during sleep and hibernate modes.

After XRES has been deasserted, at least 10 µs must elapse

before it can be reasserted.

SRES - Software Reset

A reset can be commanded under program control by setting

a bit in the software reset register. This is done either directly

by the program or indirectly by DMA access. The response to

a SRES is the same as after an IPOR reset.

Another register bit exists to disable this function.

WRES - Watchdog Timer Reset

The watchdog reset detects when the software program is no

longer being executed correctly. To indicate to the watchdog

timer that it is running correctly, the program must periodically

reset the timer. If the timer is not reset before a user-specified

amount of time, then a reset is generated.

Note

IPOR disables the watchdog function. The program must

enable the watchdog function at an appropriate point in the

code by setting a register bit. When this bit is set, it cannot be

cleared again except by an IPOR power on reset event.

Table 6-5. Analog/Digital Low Voltage Interrupt, Analog High

Voltage Interrupt

Interrupt Supply

Normal Voltage

Range

Available Trip Settings

DLVI

VDDD 1.71 V-5.5 V

1.70 V-5.45 V in 250 mV

increments

ALVI

VDDA 1.71 V-5.5 V

1.70 V-5.45 V in 250 mV

increments

AHVI

VDDA 1.71 V-5.5 V

5.75 V

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