CY8C54LP datasheet(12/117 Pages) CYPRESS

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PSoC® 5LP: CY8C54LP Family

Datasheet

Document Number: 001-84934 Rev. **

Page 12 of 117

The Cortex-M3 CPU subsystem includes these features:

ARM Cortex-M3 CPU

Programmable NVIC, tightly integrated with the CPU core

Full-featured debug and trace modules, tightly integrated with

the CPU core

Up to 128 KB of flash memory, 2 KB of EEPROM, and 32 KB

of SRAM

Cache controller

Peripheral HUB (PHUB)

DMA controller

External memory interface (EMIF)

4.1.1 Cortex-M3 Features

The Cortex-M3 CPU features include:

4-GB address space. Predefined address regions for code,

data, and peripherals. Multiple buses for efficient and

simultaneous accesses of instructions, data, and peripherals.

The Thumb®-2 instruction set, which offers ARM-level

performance at Thumb-level code density. This includes 16-bit

and 32-bit instructions. Advanced instructions include:

Bit-field control

Hardware multiply and divide

Saturation

If-Then

Wait for events and interrupts

Exclusive access and barrier

Special register access

The Cortex-M3 does not support ARM instructions.

Bit-band support for the SRAM region. Atomic bit-level write

and read operations for SRAM addresses.

Unaligned data storage and access. Contiguous storage of

data of different byte lengths.

Operation at two privilege levels (privileged and user) and in

two modes (thread and handler). Some instructions can only

be executed at the privileged level. There are also two stack

pointers: Main (MSP) and Process (PSP). These features

support a multitasking operating system running one or more

user-level processes.

Extensive interrupt and system exception support.

4.1.2 Cortex-M3 Operating Modes

The Cortex-M3 operates at either the privileged level or the user

level, and in either the thread mode or the handler mode.

Because the handler mode is only enabled at the privileged level,

there are actually only three states, as shown in Table 4-1.

At the user level, access to certain instructions, special registers,

configuration registers, and debugging components is blocked.

Attempts to access them cause a fault exception. At the

privileged level, access to all instructions and registers is

allowed.

The processor runs in the handler mode (always at the privileged

level) when handling an exception, and in the thread mode when

not.

4.1.3 CPU Registers

The Cortex-M3 CPU registers are listed in Table 4-2. Registers

R0-R15 are all 32 bits wide.

Table 4-1. Operational Level

Condition

Privileged

User

Running an exception Handler mode

Not used

Running main program Thread mode

Thread mode

Table 4-2. Cortex M3 CPU Registers

Description

R0-R12

General purpose registers R0-R12 have no

special architecturally defined uses. Most

instructions that specify a general purpose

Low Registers: Registers R0-R7 are acces-

sible by all instructions that specify a general

purpose register.

High Registers: Registers R8-R12 are acces-

sible by all 32-bit instructions that specify a

general purpose register; they are not acces-

sible by all 16-bit instructions.

R13

R13 is the stack pointer register. It is a banked

pointers: the Main Stack Pointer (MSP) and the

Process Stack Pointer (PSP). The PSP is used

only when the CPU operates at the user level in

thread mode. The MSP is used in all other

privilege levels and modes. Bits[0:1] of the SP

are ignored and considered to be 0, so the SP is

always aligned to a word (4 byte) boundary.

R14

R14 is the Link Register (LR). The LR stores the

return address when a subroutine is called.

R15

R15 is the Program Counter (PC). Bit 0 of the PC

is ignored and considered to be 0, so instructions

are always aligned to a half word (2 byte)

boundary.

xPSR

The Program status registers are divided into

three status registers, which are accessed either

together or separately:

Application Program Status Register (APSR)

holds program execution status bits such as

zero, carry, negative, in bits[27:31].

Interrupt Program Status Register (IPSR)

holds the current exception number in bits[0:8].

Execution Program Status Register (EPSR)

holds control bits for interrupt continuable and

IF-THEN instructions in bits[10:15] and

[25:26]. Bit 24 is always set to 1 to indicate

Thumb mode. Trying to clear it causes a fault

exception.

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