CY8C54LP datasheet(10/117 Pages) CYPRESS

10 / 117 page

PRELIMINARY

PSoC® 5LP: CY8C54LP Family

Datasheet

Document Number: 001-84934 Rev. **

Page 10 of 117

VBAT.

Battery supply to boost pump.

VCCA. Output of the analog core regulator or the input to

the analog core.

Requires a 1uF capacitor to VSSA. The

regulator output is not designed to drive external circuits. Note

that if you use the device with an external core regulator

(externally regulated mode), the voltage applied to this pin

must not exceed the allowable range of 1.71 V to 1.89 V.

When using the internal core regulator, (internally regulated

mode, the default), do not tie any power to this pin. For details

see Power System on page 25.

VCCD. Output of the digital core regulator or the input to the

digital core.

The two VCCD pins must be shorted together, with

the trace between them as short as possible, and a 1uF capacitor

to VSSD. The regulator output is not designed to drive external

circuits. Note that if you use the device with an external core

regulator (externally regulated mode), the voltage applied to

this pin must not exceed the allowable range of 1.71 V to

1.89 V.

When using the internal core regulator (internally

regulated mode, the default), do not tie any power to this pin. For

details see Power System on page 25.

VDDA.

Supply for all analog peripherals and analog core

regulator. VDDA must be the highest voltage present on the

device. All other supply pins must be less than or equal to

VDDA.

VDDD.

Supply for all digital peripherals and digital core

regulator. VDDD must be less than or equal to VDDA.

VSSA.

Ground for all analog peripherals.

VSSB.

Ground connection for boost pump.

VSSD.

Ground for all digital logic and I/O pins.

VDDIO0, VDDIO1, VDDIO2, VDDIO3.

Supply for I/O pins. Each

VDDIO must be tied to a valid operating voltage (1.71 V to 5.5 V),

and must be less than or equal to VDDA.

XRES (and configurable XRES)

External reset pin. Active low with internal pull-up. Pin P1[2] may

be configured to be a XRES pin; see “Nonvolatile Latches

(NVLs)” on page 18.

4. CPU

4.1 ARM Cortex-M3 CPU

The CY8C54LP family of devices has an ARM Cortex-M3 CPU

core. The Cortex-M3 is a low power 32-bit three-stage pipelined

Harvard architecture CPU that delivers 1.25 DMIPS/MHz. It is

intended for deeply embedded applications that require fast

interrupt handling features.

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