WM8903 datasheet(98/178 Pages) WOLFSON

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WM8903

Production Data

PD, Rev 4.5, June 2012

The CLK_SYS control register fields are defined in Table 61.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R20 (14h)

Clock Rates 0

MCLKDIV2

Enables divide by 2 on MCLK

0 = CLK_SYS = MCLK

1 = CLK_SYS = MCLK / 2

R21 (15h)

Clock Rates 1

CLK_SRC_SEL

SYSCLK Source Select

0 = MCLK

1 = FLL output

R22 (16h)

Clock Rates 2

CLK_SYS_ENA

System Clock enable

0 = Disabled

1 = Enabled

CLK_DSP_ENA

DSP Clock enable

0 = Disabled

1 = Enabled

TO_ENA

Zero Cross timeout enable

0 = Disabled

1 = Enabled

R108 (6Ch)

Write

Sequencer 0

WSMD_CLK_E

Write Sequencer / Mic Detect Clock

Enable.

0 = Disabled

1 = Enabled

Table 61 MCLK and CLK_SYS Control

CONTROL INTERFACE CLOCKING

has been set to 1, then a Master Clock must be present for control register Read/Write operations. If

CLK_SYS_ENA = 1 and MCLK is not present, then register access will be unsuccessful. (Note that

read/write access to register R22, containing CLK_SYS_ENA, is always possible.)

If it cannot be assured that MCLK is present when accessing the register map, then it is required to

set CLK_SYS_ENA = 0 to ensure correct operation.

It is possible to use the WM8903 analogue bypass paths to the differential line outputs (LON/LOP and

RON/ROP) without MCLK. Note that MCLK is always required when using HPOUTL, HPOUTR,

LINEOUTL or LINEOUTR.

AUTOMATIC CLOCKING CONFIGURATION

The WM8903 supports a wide range of standard audio sample rates from 8kHz to 96kHz. The

Automatic Clocking Configuration mode simplifies the configuration of the clock dividers in the

WM8903 by deriving most of the necessary parameters from a minimum number of user registers.

The SAMPLE_RATE field selects the sample rate, fs, of the ADC and DAC. Note that the same

sample rate always applies to the ADC and DAC.

The CLK_SYS_RATE and CLK_SYS_MODE fields must be set according to the ratio of CLK_SYS to

fs. (Note that the internal clock CLK_SYS is derived from MCLK as controlled by MCLKDIV2). When

these fields are set correctly, the Sample Rate Decoder circuit automatically determines the clocking

configuration for all other circuits within the WM8903.

WM8903 Datasheet(PDF) 98 Page - Wolfson Microelectronics plc

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