DSPIC33FJ09GS302 datasheet(83/352 Pages) MICROCHIP

83 / 352 page

 2011-2012 Microchip Technology Inc.

DS75018C-page 83

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302

FIGURE 6-2:

SYSTEM RESET TIMING

Reset

Run

Device Status

VDD

VPOR

VBOR

POR

BOR

SYSRST

TPWRT

TPOR

TBOR

Oscillator Clock

TOSCD

TOST

TLOCK

Time

FSCM

TFSCM

Note 1:

POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the

VPOR threshold and the delay, TPOR, has elapsed.

BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the VBOR threshold and the

delay, TBOR, has elapsed. The delay, TBOR, ensures the voltage regulator output becomes stable.

PWRT Timer: The programmable Power-up Timer continues to hold the processor in Reset for a specific period of time (TPWRT)

after a BOR. The delay, TPWRT, ensures that the system power supplies have stabilized at the appropriate level for full-speed oper-

ation. After the delay, TPWRT has elapsed and the SYSRST becomes inactive, which in turn, enables the selected oscillator to start

generating clock cycles.

Oscillator Delay: The total delay for the clock to be ready for various clock source selections is given in Table 6-1. Refer to

Section 8.0 “Oscillator Configuration” for more information.

When the oscillator clock is ready, the processor begins execution from location, 0x000000. The user application programs a GOTO

instruction at the Reset address, which redirects program execution to the appropriate start-up routine.

If the Fail-Safe Clock Monitor (FSCM) is enabled, it begins to monitor the system clock when the system clock is ready and the delay,

TFSCM, has elapsed.

TABLE 6-2:

OSCILLATOR PARAMETERS

Symbol

Parameter

Value

VPOR

POR threshold

1.8V nominal

TPOR

POR extension time

s maximum

VBOR

BOR threshold

2.65V nominal

TBOR

BOR extension time

100

s maximum

TPWRT

Programmable

Power-up Time delay

0-128 ms nominal

TFSCM

Fail-Safe Clock Mon-

itor delay

900

s maximum

Note:

When the device exits the Reset con-

dition (begins normal operation), the

device operating parameters (voltage,

frequency, temperature, etc.) must be

within their operating ranges; otherwise,

the device may not function correctly.

The user application must ensure that

the delay between the time power is first

applied, and the time SYSRST becomes

inactive, is long enough to get all

operating

parameters

within

the

specification.

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