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DSPIC30F4012 Datasheet(PDF) 233 Page - Microchip Technology |
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DSPIC30F4012 Datasheet(HTML) 233 Page - Microchip Technology |
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233 / 238 page ![]() © 2010 Microchip Technology Inc. DS70135G-page 233 dsPIC30F4011/4012 U UART Address Detect Mode ............................................... 123 Alternate I/O.............................................................. 121 Auto-Baud Support ................................................... 124 Baud Rate Generator................................................ 123 Disabling ................................................................... 121 Enabling and Setting Up ........................................... 121 Loopback Mode ........................................................ 123 Module Overview ...................................................... 119 Operation During CPU Sleep and Idle Modes .......... 124 Receiving Data.......................................................... 122 In 8-bit or 9-bit Data Mode ................................ 122 Interrupt ............................................................ 122 Receive Buffer (UxRCB) ................................... 122 Reception Error Handling.......................................... 122 Framing Error (FERR) ...................................... 123 Idle Status ......................................................... 123 Parity Error (PERR) .......................................... 123 Receive Break .................................................. 123 Receive Buffer Overrun Error (OERR Bit) ........ 122 Setting Up Data, Parity and Stop Bit Selections ....... 121 Transmitting Data...................................................... 121 Break ................................................................ 122 In 8-bit Data Mode ............................................ 121 In 9-bit Data Mode ............................................ 121 Interrupt ............................................................ 122 Transmit Buffer (UxTXB) .................................. 121 UART1 Register Map................................................ 125 UART2 Register Map................................................ 125 Unit ID Locations............................................................... 149 Universal Asynchronous Receiver Transmitter Module (UART)...................................... 119 W Wake-up from Sleep ......................................................... 149 Wake-up from Sleep and Idle ............................................. 47 Watchdog Timer (WDT) ............................................ 149, 159 Enabling and Disabling ............................................. 159 Operation .................................................................. 159 WWW Address.................................................................. 235 WWW, On-Line Support ....................................................... 8 |
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