DSPIC30F4012 datasheet(110/238 Pages) MICROCHIP

110 / 238 page

dsPIC30F4011/4012

DS70135G-page 110

16.2

Framed SPI Support

The module supports a basic framed SPI protocol in

Master or Slave mode. The control bit, FRMEN,

enables framed SPI support and causes the SS1 pin to

perform the frame synchronization pulse (FSYNC)

function. The control bit, SPIFSD, determines whether

the SS1 pin is an input or an output (i.e., whether the

module receives or generates the frame synchroniza-

tion pulse). The frame pulse is an active-high pulse for

a single SPI clock cycle. When frame synchronization

is enabled, the data transmission starts only on the

subsequent transmit edge of the SPI clock.

FIGURE 16-1:

SPI BLOCK DIAGRAM

FIGURE 16-2:

SPI MASTER/SLAVE CONNECTION

Read

Write

Internal

Data Bus

SDI1

SDO1

SS1

SCK1

SPI1SR

SPI1BUF

bit 0

Shift

Clock

Edge

Select

FCY

Primary

1, 4, 16, 64

Enable Master Clock

Prescaler

Secondary

Prescaler

1, 2, 4, 6, 8

Transmit

SPI1BUF

Receive

SS1 and

Control

Clock

Control

FSYNC

Serial Input Buffer

(SPI1BUF)

Shift Register

(SPI1SR)

MSb

LSb

SDO1

SDI1

PROCESSOR 1

SCK1

SPI Master

Serial Input Buffer

(SPI1BUF)

LSb

MSb

SDI1

SDO1

PROCESSOR 2

SCK1

SPI Slave

Serial Clock

Shift Register

(SPI1SR)

DSPIC30F4012 Datasheet(PDF) 110 Page - Microchip Technology

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