DSPIC30F4012 datasheet(111/238 Pages) MICROCHIP

111 / 238 page

DS70135G-page 111

dsPIC30F4011/4012

16.3

Slave Select Synchronization

The SS1 pin allows a Synchronous Slave mode. The

SPI must be configured in SPI Slave mode, with SS1

pin control enabled (SSEN = 1). When the SS1 pin is

low, transmission and reception are enabled and the

SDO1 pin is driven. When SS1 pin goes high, the

SDO1 pin is no longer driven. Also, the SPI module is

resynchronized and all counters/control circuitry are

reset. Therefore, when the SS1 pin is asserted low

again, transmission/reception will begin at the MSb,

even if SS1 had been deasserted in the middle of a

transmit/receive.

16.4

SPI Operation During CPU Sleep

Mode

During Sleep mode, the SPI module is shut down. If

the CPU enters Sleep mode while an SPI transaction

is in progress, then the transmission and reception is

aborted.

The transmitter and receiver will stop in Sleep mode.

However, register contents are not affected by

entering or exiting Sleep mode.

16.5

SPI Operation During CPU Idle

Mode

When the device enters Idle mode, all clock sources

remain functional. The SPISIDL bit (SPI1STAT<13>)

selects if the SPI module will stop or continue on Idle.

If SPISIDL = 0, the module will continue to operate

when the CPU enters Idle mode. If SPISIDL = 1, the

module will stop when the CPU enters Idle mode.

DSPIC30F4012 Datasheet(PDF) 111 Page - Microchip Technology