DSPIC30F4012 datasheet(142/238 Pages) MICROCHIP

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dsPIC30F4011/4012

DS70135G-page 142

20.4

Programming the Start of the

Conversion Trigger

The conversion trigger terminates acquisition and starts

the requested conversions.

The SSRC<2:0> bits select the source of the

conversion trigger.

The SSRC bits provide for up to five alternate sources

of conversion trigger.

When SSRC<2:0> = 000, the conversion trigger is

under software control. Clearing the SAMP bit causes

the conversion trigger.

When SSRC<2:0> = 111 (Auto-Start mode), the con-

version trigger is under A/D clock control. The SAMC

bits select the number of A/D clocks between the start

of acquisition and the start of conversion. This provides

the fastest conversion rates on multiple channels.

SAMC must always be at least one clock cycle.

Other trigger sources can come from timer modules,

motor control PWM module or external interrupts.

20.5

Aborting a Conversion

Clearing the ADON bit during a conversion aborts the

current conversion and stops the sampling sequencing.

The ADCBUFx is not updated with the partially com-

pleted A/D conversion sample. That is, the ADCBUFx

will continue to contain the value of the last completed

conversion (or the last value written to the ADCBUFx

If the clearing of the ADON bit coincides with an

auto-start, the clearing has a higher priority.

After the A/D conversion is aborted, a 2 TAD wait is

required before the next sampling may be started by

setting the SAMP bit.

If sequential sampling is specified, the A/D continues at

the next sample pulse, which corresponds with the next

channel converted. If simultaneous sampling is speci-

fied, the A/D continues with the next multichannel

group conversion sequence.

20.6

Selecting the A/D Conversion

Clock

The A/D conversion requires 12 TAD. The source of the

A/D conversion clock is software selected using a 6-bit

counter. There are 64 possible options for TAD.

EQUATION 20-1:

A/D CONVERSION CLOCK

The internal RC oscillator is selected by setting the

ADRC bit.

For correct A/D conversions, the A/D conversion clock

(TAD) must be selected to ensure a minimum TAD time

of 83.33 nsec (for VDD = 5V). Refer to Section 24.0

“Electrical Characteristics” for minimum TAD under

other operating conditions.

Example 20-1 shows a sample calculation for the

ADCS<5:0> bits, assuming a device operating speed

of 30 MIPS.

EXAMPLE 20-1:

A/D CONVERSION CLOCK

CALCULATION

Note:

To operate the ADC at the maximum

specified conversion speed, the auto-

convert trigger option should be selected

(SSRC = 111) and the auto-sample

time

bits should be set to ‘1’ TAD

(SAMC = 00001). This configuration gives

a total conversion period (sample +

convert) of 13 TAD.

The use of any other conversion trigger

results

additional

TAD

cycles

synchronize the external event to the

ADC.

TAD = TCY * (0.5 * (ADCS<5:0> + 1))

ADCS<5:0> = 2

– 1

TAD

TCY

TAD = 154 nsec

ADCS<5:0> = 2

– 1

TAD

TCY

TCY = 33 nsec (30 MIPS)

= 2 •

– 1

154 nsec

33 nsec

= 8.33

Therefore,

Set ADCS<5:0> = 9

Actual TAD =

(ADCS<5:0> + 1)

TCY

(9 + 1)

33 nsec

= 165 nsec

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