DSPIC30F4012 datasheet(147/238 Pages) MICROCHIP

147 / 238 page

DS70135G-page 147

dsPIC30F4011/4012

20.9

Module Power-Down Modes

The module has 3 internal power modes. When the

ADON bit is ‘1’, the module is in Active mode; it is fully

powered and functional. When ADON is ‘0’, the module

is in Off mode. The digital and analog portions of the

circuit are disabled for maximum current savings. In

order to return to the Active mode from Off mode, the

user must wait for the ADC circuitry to stabilize.

20.10 A/D Operation During CPU Sleep

and Idle Modes

20.10.1

A/D OPERATION DURING CPU

SLEEP MODE

When the device enters Sleep mode, all clock sources

to the module are shut down and stay at logic ‘0’.

If Sleep occurs in the middle of a conversion, the

conversion is aborted. The converter will not continue

with a partially completed conversion on exit from

Sleep mode.

entering or leaving Sleep mode.

The ADC module can operate during Sleep mode if the

A/D clock source is set to RC (ADRC = 1). When the

RC clock source is selected, the ADC module waits

one instruction cycle before starting the conversion.

This allows the SLEEP instruction to be executed,

which eliminates all digital switching noise from the

conversion. When the conversion is complete, the

DONE bit is set and the result is loaded into the

ADCBUFx register.

If the A/D interrupt is enabled, the device wakes up

from Sleep. If the A/D interrupt is not enabled, the ADC

module is then turned off, although the ADON bit

remains set.

20.10.2

A/D OPERATION DURING CPU IDLE

MODE

The ADSIDL bit selects if the module stops on Idle or

continues on Idle. If ADSIDL = 0, the module continues

operation on assertion of Idle mode. If ADSIDL = 1, the

module stops on Idle.

20.11 Effects of a Reset

A device Reset forces all registers to their Reset state.

This forces the ADC module to be turned off, and any

conversion and acquisition sequence is aborted. The

values that are in the ADCBUFx registers are not

modified. The A/D Result register contains unknown

data after a Power-on Reset.

20.12 Output Formats

The A/D result is 10 bits wide. The data buffer RAM is

also 10 bits wide. The 10-bit data can be read in one of

four different formats. The FORM<1:0> bits select the

format. Each of the output formats translates to a 16-bit

result on the data bus.

Write data will always be in right justified (integer)

format.

FIGURE 20-4:

A/D OUTPUT DATA FORMATS

RAM Contents:

d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

Read to Bus:

Signed Fractional (1.15)

d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

000000

Fractional (1.15)

d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

000000

Signed Integer

d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

Integer

d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

DSPIC30F4012 Datasheet(PDF) 147 Page - Microchip Technology

DSPIC30F4012 Datasheet(HTML) 147 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL