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MACH211SP-7VC Datasheet(PDF) 20 Page - Advanced Micro Devices

Part # MACH211SP-7VC
Description  High-Density EE CMOS Programmable Logic
PDF  37 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

MACH211SP-7VC Datasheet(HTML) 20 Page - Advanced Micro Devices

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MACH211SP-14/18/24 (Ind)
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Unit
CIN
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25°C
f = 1 MHz
6pF
COUT
Output Capacitance
VOUT = 2.0 V
8
pF
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
-14
-18
-24
Unit
Min
Max
Min
Max
Min
Max
tPD
Input, I/O, or Feedback to Combinatorial Output
(Note 3)
14.5
18
24
ns
tS
Setup Time from Input, I/O, or
Feedback to Clock
D-type
8.5
12
16
ns
T-type
10
13.5
17
ns
tH
Register Data Hold Time
0
0
0
ns
tCO
Clock to Output (Note 3)
10
12
14.5
ns
tWL
Clock Width
LOW
7.5
7.5
10
ns
tWH
HIGH
7.5
7.5
10
ns
fMAX
Maximum
Frequency
(Note 1)
External
Feedback
1/(tS + tCO)
D-type
53
40
32
MHz
T-type
50
38
30.5
MHz
Internal Feedback (fCNT)
D-type
61.5
53
38
MHz
T-type
57
44
34.5
MHz
No
Feedback
1/(tWL + tWH)
66.5
66.5
50
MHz
tSL
Setup Time from Input, I/O, or Feedback to Gate
8.5
12
16
ns
tHL
Latch Data Hold Time
0
0
0
ns
tGO
Gate to Output
12
13.5
14.5
ns
tGWL
Gate Width LOW
7.5
7.5
10
ns
tPDL
Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch
17
20.5
26.5
ns
tSIR
Input Register Setup Time
2.5
2.5
2.5
ns
tHIR
Input Register Hold Time
3
3.5
4
ns
tICO
Input Register Clock to Combinatorial Output
18
22
28
ns
tICS
Input Register Clock to Output Register
Setup
D-type
14.5
18
24
ns
T-type
16
19.5
25.5
ns
tWICL
Input Register Clock Width
LOW
7.5
7.5
10
ns
tWICH
HIGH
7.5
7.5
10
ns
fMAXIR
Maximum Input Register
Frequency
1/(tWICL + tWICH)
66.5
66.5
50
MHz
tSIL
Input Latch Setup Time
2.5
2.5
2.5
ns
tHIL
Input Latch Hold Time
3
3.5
4
ns
tIGO
Input Latch Gate to Combinatorial Output
20.5
24
30
ns



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