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MACH211SP-7VC Datasheet(PDF) 14 Page - Advanced Micro Devices

Part # MACH211SP-7VC
Description  High-Density EE CMOS Programmable Logic
PDF  37 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

MACH211SP-7VC Datasheet(HTML) 14 Page - Advanced Micro Devices

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14
MACH211SP-12/15/20 (Com’l)
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Unit
CIN
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25°C
f = 1 MHz
6pF
COUT
Output Capacitance
VOUT = 2.0 V
8
pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
-12
-15
-20
Unit
Min
Max
Min
Max
Min
Max
tPD
Input, I/O, or Feedback to Combinatorial Output
(Note 3)
12
15
20
ns
tS
Setup Time from Input, I/O, or
Feedback to Clock
D-type
7
10
13
ns
T-type
8
11
14
ns
tH
Register Data Hold Time
0
0
0
ns
tCO
Clock to Output (Note 3)
8
10
12
ns
tWL
Clock Width
LOW
6
6
8
ns
tWH
HIGH
6
6
8
ns
fMAX
Maximum
Frequency
(Note 1)
External
Feedback
1/(tS + tCO)
D-type
66.7
50
40
MHz
T-type
62.5
47.6
38.5
MHz
Internal Feedback (fCNT)
D-type
83.3
66.6
50
MHz
T-type
76.9
62.5
47.6
MHz
No
Feedback
1/(tWL + tWH)
83.3
83.3
62.5
MHz
tSL
Setup Time from Input, I/O, or Feedback to Gate
7
10
13
ns
tHL
Latch Data Hold Time
0
0
0
ns
tGO
Gate to Output
10
11
12
ns
tGWL
Gate Width LOW
6
6
8
ns
tPDL
Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch
14
17
22
ns
tSIR
Input Register Setup Time
2
2
2
ns
tHIR
Input Register Hold Time
2
2.5
3
ns
tICO
Input Register Clock to Combinatorial Output
15
18
23
ns
tICS
Input Register Clock to Output Register
Setup
D-type
12
15
20
ns
T-type
13
16
21
ns
tWICL
Input Register Clock Width
LOW
6
6
8
ns
tWICH
HIGH
6
6
8
ns
fMAXIR
Maximum Input Register
Frequency
1/(tWICL + tWICH)
83.3
83.3
62.5
MHz
tSIL
Input Latch Setup Time
2
2
2
ns
tHIL
Input Latch Hold Time
2
2.5
3
ns



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