JS28F640P33TF70 datasheet(17/88 Pages) NUMONYX

17 / 88 page

Datasheet

Jul 2011

Order Number:208034-04

P33-65nm SBC

Write

0x40

Word Program

Setup

First cycle of a 2-cycle programming command; prepares the CUI for a write

operation. On the next write cycle, the address and data are latched and the

WSM executes the programming algorithm at the addressed location. During

program operations, the device responds only to Read Status Register and

Program Suspend commands. CE# or OE# must be toggled to update the

Status Register in asynchronous read. CE# or ADV# must be toggled to

update the SR Data for synchronous Non-array reads. The Read Array

command must be issued to read array data after programming has finished.

0xE8

Buffered Program

This command loads a variable number of words up to the buffer size of 256

words onto the program buffer.

0xD0

Buffered Program

Confirm

The confirm command is issued after the data streaming for writing into the

buffer is done. This instructs the WSM to perform the Buffered Program

algorithm, writing the data from the buffer to the flash memory array.

0x80

BEFP Setup

First cycle of a 2-cycle command; initiates the BEFP mode. The CUI then

waits for the BEFP Confirm command, 0xD0, that initiates the BEFP

algorithm. All other commands are ignored when BEFP mode begins.

0xD0

BEFP Confirm

If the previous command was BEFP Setup (0x80), the CUI latches the

address and data, and prepares the device for BEFP mode.

Erase

0x20

Block Erase Setup

First cycle of a 2-cycle command; prepares the CUI for a block-erase

operation. The WSM performs the erase algorithm on the block addressed by

the Erase Confirm command. If the next command is not the Erase Confirm

(0xD0) command, the CUI sets Status Register bits SR [5,4], and places the

device in Read Status Register mode.

0xD0

Block Erase Confirm

If the first command was Block Erase Setup (0x20), the CUI latches the

address and data, and the WSM erases the addressed block. During block-

erase operations, the device responds only to Read Status Register and Erase

Suspend commands. CE# or OE# must be toggled to update the Status

SR Data for synchronous Non-array reads.

Suspend

0xB0

Program or Erase

Suspend

This command issued to any device address initiates a suspend of the

currently-executing program or block erase operation. The Status Register

indicates successful suspend operation by setting either SR.2 (program

suspended) or SR 6 (erase suspended), along with SR.7 (ready). The WSM

remains in the suspend mode regardless of control signal states (except for

RST# asserted).

0xD0

Suspend Resume

This command issued to any device address resumes the suspended program

or block-erase operation.

Protection

0x60

Block lock Setup

First cycle of a 2-cycle command; prepares the CUI for block lock

configuration changes. If the next command is not Block Lock (0x01), Block

Unlock (0xD0), or Block Lock-Down (0x2F), the CUI sets SR.5 and SR.4,

indicating a command sequence error.

0x01

Block lock

If the previous command was Block Lock Setup (0x60), the addressed block

is locked.

0xD0

Unlock Block

If the previous command was Block Lock Setup (0x60), the addressed block

is unlocked. If the addressed block is in a lock-down state, the operation has

no effect.

0x2F

Lock-Down Block

If the previous command was Block Lock Setup (0x60), the addressed block

is locked down.

0xC0

Protection program

setup

First cycle of a 2-cycle command; prepares the device for a OTP Register or

Lock Register program operation. The second cycle latches the register

address and data, and starts the programming algorithm to program data

into the OTP array.

Table 5:

Command Codes and Definitions (Sheet 2 of 3)

Mode

Code

Device Mode

Description

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