JS28F640P33TF70 datasheet(20/88 Pages) NUMONYX

20 / 88 page

P33-65nm

Datasheet

Jul 2011

Order Number: 208034-04

7.0

Read Operation

The device can be in any of four read states: Read Array, Read Identifier, Read Status

or Read Query. Upon power-up, or after a reset, the device defaults to Read Array

mode. To change the read state, the appropriate read command must be written to the

device (see Section 6.2, “Device Command Bus Cycles” on page 18). The following

sections describe read-mode operations in detail.

The device supports two read modes: asynchronous page mode and synchronous burst

mode. Asynchronous page mode is the default read mode after device power-up or a

reset. The RCR must be configured to enable synchronous burst reads of the flash

memory array (see Section 11.1, “Read Configuration Register” on page 33).

7.1

Asynchronous Page-Mode Read

Following a device power-up or reset, asynchronous page mode is the default read

mode and the device is set to Read Array mode. However, to perform array reads after

any other device operation (e.g. write operation), the Read Array command must be

issued in order to read from the flash memory array.

To perform an asynchronous page-mode read, an address is driven onto the address

bus, and CE# and ADV# are asserted. WE# and RST# must already have been

deasserted. WAIT is deasserted during asynchronous page mode. ADV# can be driven

high to latch the address, or it must be held low throughout the read cycle. CLK is not

used for asynchronous page-mode reads, and is ignored. If only asynchronous reads

are to be performed, CLK should be tied to a valid VIH or VILlevel, WAIT signal can be

floated and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after an

initial access time tAVQV delay. (see Section 15.0, “AC Characteristics” on page 48).

In asynchronous page mode, eight data words are “sensed” simultaneously from the

flash memory array and loaded into an internal page buffer. The buffer word

corresponding to the initial address on the Address bus is driven onto DQ[15:0] after

the initial access delay. The lowest four address bits determine which word of the

16-word page is output from the data buffer at any given time.

7.2

Synchronous Burst-Mode Read

To perform a synchronous burst-read, an initial address is driven onto the address bus,

and CE# and ADV# are asserted. WE# and RST# must already have been deasserted.

ADV# is asserted, and then deasserted to latch the address. Alternately, ADV# can

remain asserted throughout the burst access, in which case the address is latched on

the next valid CLK edge while ADV# is asserted.

During synchronous array and non-array read modes, the first word is output from the

data buffer on the next valid CLK edge after the initial access latency delay (see Section

11.1.2, “Latency Count (RCR[13:11])” on page 34). Subsequent data is output on valid

CLK edges following a minimum delay. However, for a synchronous non-array read, the

same word of data will be output on successive clock edges until the burst length

requirements are satisfied. Refer to the following waveforms for more detailed

information:

• Figure 20, “Synchronous Single-Word Array or Non-array Read Timing” on page 52

• Figure 21, “Continuous Burst Read, showing an Output Delay Timing” on page 53

• Figure 22, “Synchronous Burst-Mode Four-Word Read Timing” on page 53

JS28F640P33TF70 Datasheet(PDF) 20 Page - Numonyx B.V

JS28F640P33TF70 Datasheet(HTML) 20 Page - Numonyx B.V

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

Datasheet Download

Link URL