CS4215 datasheet(17/52 Pages) CIRRUS

17 / 52 page

Lower output level to

maximum attenuation

Mute the speaker output

Set D/C low

Codec programmed for

Master mode & ITS=0?

Set external controller to

drive SCLK and FSYNC

into the codec

Send valid control information

with CLB=0

Read back and verify control information.

Mask off reserved bits

n = 5

Send valid control information

with CLB=0

n = n - 1

CLB=0?

Set CLB=1 and send at least

two more frames of valid

control information

Set external controller to

receive SCLK and FSYNC

from the codec

Is codec

programmed for

Master mode?

Set D/C high.

Transmit/receive data with attenuated outputs

and muted speaker for 194 FSYNC cycles

while codec executes offset calibration

Transmit/receive audio data

with desired level settings

n = 0?

Poll for CLB=0?

Wait at least 12 SCLK

periods for FSYNC and

SCLK to three-state

This is a software design choice,

not a run-time conditional branch.

This will cause the codec to

ignore any further bus activity.

The SDOUT pin will be held in

the high impedance state after

transmitting 1 frame with CLB=1

Figure 11. Control Mode Flow Chart

CS4215

DS76F2

CS4215 Datasheet(PDF) 17 Page - Cirrus Logic

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