CS4215 datasheet(19/52 Pages) CIRRUS

19 / 52 page

BIT

NAME

VALUE

FUNCTION

XEN

Transmitter Enable

Enable the serial data output.

Disable (high-impedance state) serial data output.

XCLK

Transmit Clock

R Receive SCLK and FSYNC from external source

SLAVE Mode

Generate SCLK and FSYNC

MASTER Mode

BSEL1-0

Select Bit Rate

0 0

0 1

1 0

1 1

64 bits per frame.

128 bits per frame.

256 bits per frame.

Reserved.

MCK2-0

Clock Source Select

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

SCLK is master clock, 256 bits per frame.

BSEL must equal 2, and XCLK must equal 0.

XTAL1, 24.576 MHz, is clock source.

XTAL2, 16.9344 MHz, is clock source.

CLKIN is clock source, and must be 256xFs.

CLKIN is clock source, DFR2-0 select sample

frequency.

ITS

Immediate Three-

State

R SCLK and FSYNC three-state up to 12 clocks

after D/C goes low.

SCLK and FSYNC three-state immediately

after D/C goes low.

Control Time Slot 3, Serial Port Control Register

ITS

MCK2 MCK1 MCK0 BSEL1 BSEL0 XCLK

XEN

00001001

Reset (R)

Control Time Slot 4, Test Register

TEST

ENL

DAD

00000000

Reset (R)

BIT

NAME

VALUE

FUNCTION

DAD

Loopback Mode

R Digital-Digital Loopback.

Digital-Analog-Digital Loopback.

ENL

Enable Loopback

Testing

R Disable.

Enable.

TEST

Test bits

The TEST bits must be written as zero, otherwise

special factory test modes may be invoked.

CS4215

DS76F2

CS4215 Datasheet(PDF) 19 Page - Cirrus Logic

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