EPF8282AV datasheet(23/62 Pages) ALTERA

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Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet

Table 5 lists the source of the peripheral control signal for each FLEX 8000

device by row.

Output

Configuration

This section discusses slew-rate control and MultiVolt I/O interface

operation for FLEX 8000 devices.

Slew-Rate Control

The output buffer in each IOE has an adjustable output slew rate that can

be configured for low-noise or high-speed performance. A slow slew rate

reduces system noise by slowing signal transitions, adding a maximum

delay of 3.5 ns. The slow slew-rate setting affects only the falling edge of

a signal. The fast slew rate should be used for speed-critical outputs in

systems that are adequately protected against noise. Designers can specify

the slew rate on a pin-by-pin basis during design entry or assign a default

slew rate to all pins on a global basis.

f For more information on high-speed system design, go to Application

Note 75 (High-Speed Board Designs).

Table 5. Row Sources of FLEX 8000 Peripheral Control Signals

Peripheral

Control Signal

EPF8282A

EPF8282AV

EPF8452A

EPF8636A

EPF8820A

EPF81188A

EPF81500A

CLK0

Row A

Row E

CLK1/OE1

Row B

Row C

Row B

CLR0

Row A

Row B

Row F

CLR1/OE0

Row B

Row C

Row D

Row C

OE2

Row A

Row D

Row A

OE3

Row B

Row A

OE4

–––––

Row B

OE5

–––––

Row C

OE6

–––––

Row D

OE7

–––––

Row D

OE8

–––––

Row E

OE9

–––––

Row F

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