EPF8282AV datasheet(32/62 Pages) ALTERA

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Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet

Figure 18. Output Drive Characteristics of EPF8282AV Devices

Timing Model

The continuous, high-performance FastTrack Interconnect routing

structure ensures predictable performance and accurate simulation and

timing analysis. This predictable performance contrasts with that of

FPGAs, which use a segmented connection scheme and hence have

unpredictable performance. Timing simulation and delay prediction are

available with the MAX+PLUS II Simulator and Timing Analyzer, or with

industry-standard EDA tools. The Simulator offers both pre-synthesis

functional simulation to evaluate logic design accuracy and post-

synthesis timing simulation with 0.1-ns resolution. The Timing Analyzer

provides point-to-point timing delay information, setup and hold time

prediction, and device-wide performance analysis.

Tables 17 through 20 describe the FLEX 8000 timing parameters and their

symbols.

100

CC = 3.3 V

IOL

IOH

Room Temperature

Output Voltage (V)

Typical IO

Output

Current (mA)

EPF8282AV Datasheet(PDF) 32 Page - Altera Corporation