EPF8282AV datasheet(4/62 Pages) ALTERA

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Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet

FLEX 8000 devices contain an optimized microprocessor interface that

permits the microprocessor to configure FLEX 8000 devices serially, in

parallel, synchronously, or asynchronously. The interface also enables the

microprocessor to treat a FLEX 8000 device as memory and configure the

device by writing to a virtual memory location, making it very easy for the

designer to create configuration software.

The FLEX 8000 family is supported by Altera’s MAX+PLUS II

development system, a single, integrated package that offers schematic,

text—including the Altera Hardware Description Language (AHDL),

VHDL, and Verilog HDL—and waveform design entry, compilation and

logic synthesis, simulation and timing analysis, and device programming.

The MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, library of

parameterized modules (LPM), VHDL, Verilog HDL, and other interfaces

for additional design entry and simulation support from other industry-

standard PC- and UNIX workstation-based EDA tools. The

MAX+PLUS II software runs on Windows-based PCs and Sun

SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000

workstations.

The MAX+PLUS II software interfaces easily with common gate array

EDA tools for synthesis and simulation. For example, the MAX+PLUS II

software can generate Verilog HDL files for simulation with tools such as

Cadence Verilog-XL. Additionally, the MAX+PLUS II software contains

EDA libraries that use device-specific features such as carry chains, which

are used for fast counter and arithmetic functions. For instance, the

Synopsys Design Compiler library supplied with the MAX+PLUS II

development system includes DesignWare functions that are optimized

for the FLEX 8000 architecture.

f For more information on the MAX+PLUS II software, go to the

MAX+PLUS II Programmable Logic Development System & Software Data

Sheet.

Functional

Description

The FLEX 8000 architecture incorporates a large matrix of compact

building blocks called logic elements (LEs). Each LE contains a 4-input

LUT that provides combinatorial logic capability and a programmable

of the LE provides highly efficient logic implementation.

Eight LEs are grouped together to form a logic array block (LAB). Each

FLEX 8000 LAB is an independent structure with common inputs,

interconnections, and control signals. The LAB architecture provides a

coarse-grained structure for high device performance and easy routing.

EPF8282AV Datasheet(PDF) 4 Page - Altera Corporation

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