EPF8282AV datasheet(26/62 Pages) ALTERA

26 / 62 page

Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet

f FordetailedinformationonJTAGoperationinFLEX 8000devices,referto

Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera

Devices).

Generic Testing

Each FLEX 8000 device is functionally tested and specified by Altera.

Complete testing of each configurable SRAM bit and all logic

functionality ensures 100% configuration yield. AC test measurements for

FLEX 8000 devices are made under conditions equivalent to those shown

in Figure 15. Designers can use multiple test patterns to configure devices

during all stages of the production flow.

Table 8. JTAG Timing Parameters & Values

Symbol

Parameter

EPF8282A

EPF8282AV

EPF8636A

EPF8820A

EPF81500A

Unit

Min

Max

tJCP

TCK

clock period

100

tJCH

TCK

clock high time

tJCL

TCK

clock low time

tJPSU

JTAG port setup time

tJPH

JTAG port hold time

tJPCO

JTAG port clock to output

tJPZX

JTAG port high-impedance to valid output

tJPXZ

JTAG port valid output to high-impedance

tJSSU

Capture register setup time

tJSH

Capture register hold time

tJSCO

Update register clock to output

tJSZX

Update register high-impedance to valid output

tJSXZ

Update register valid output to high-impedance

EPF8282AV Datasheet(PDF) 26 Page - Altera Corporation

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