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WM8580AGEFTV Datasheet(PDF) 53 Page - Wolfson Microelectronics plc

Part # WM8580AGEFTV
Description  Multichannel CODEC with S/PDIF Transceiver
PDF  106 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8580AGEFTV Datasheet(HTML) 53 Page - Wolfson Microelectronics plc

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Production Data
WM8580A
w
PD, Rev 4.9, November 2013
53
PHASE-LOCKED LOOPS AND S/PDIF CLOCKING (SOFTWARE MODE)
The WM8580A is equipped with two independent phase-locked loop clock generators and a
comprehensive clocking scheme which provides maximum flexibility and function and many
configurable routing possibilities for the user in software mode. An overview of the software mode
clocking scheme is shown in Figure 38.
PLL_A
( R = f2 / f1 )
DIV
DIV
f1
OSCCLK
f2
DIV
PLLACLK
OSC
CLKOUT
XOUT
XIN
S/PDIF RX
PLL_B
( R = f2 / f1 )
DIV
f1
f2
DIV
DIV
PLLBCLK
PLLBCLK
OSCCLK
PLLACLK
MCLK
PLLBCLK
OSCCLK
PLLACLK
CLK2
CLK1
Figure 38 PLL and Clock Select Circuit
OSCILLATOR
The function of the oscillator is to generate the OSCCLK oscillator clock signal. This signal may be
used as:
The clock source for the PLLs.
A selectable clock source for the MCLK pin, when the pin is configured as an output.
A selectable clock source for the CLKOUT pin, when enabled.
Whenever the PLLs or the S/PDIF receiver is enabled, the OSCCLK signal must be present to enable
the PLLs to generate the necessary clock signals.
The oscillator uses a Pierce type oscillator drive circuit. This circuit requires an external crystal and
appropriate external loading capacitors. The oscillator circuit contains a bias generator within the
WM8580A and hence an external bias resistor is not required. Crystal frequencies between 10 and
14.4MHz or 16.28MHz and 27MHz can be used in software mode. In this case the oscillator XOUT
must be powered up using the OSCPD bit. The recommended circuit is shown in the recommended
components diagram, please refer to Figure 55.
Alternatively, an external CMOS compatible clock signal can be applied to the XIN pin in the absence
of a crystal. This is not recommended when using the PLL as the PLL requires a jitter-free OSCCLK
signal for optimum performance. In this case the oscillator XOUT can be powered down using the
OSCPD bit.



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