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WM8580AGEFTV Datasheet(PDF) 67 Page - Wolfson Microelectronics plc |
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WM8580AGEFTV Datasheet(HTML) 67 Page - Wolfson Microelectronics plc |
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67 / 106 page  Production Data WM8580A w PD, Rev 4.9, November 2013 67 REGISTER ADDRESS BIT LABEL CHANNEL STATUS BIT DEFAULT DESCRIPTION R46 SPDRXCHAN 3 2Eh (read-only) 3:0 SRCNUM [3:0] 19:16 - Indicates S/PDIF source number. Refer to S/PDIF specification IEC60958-3 for details. 5:4 CHNUM1[1:0] 21:20 - Channel number for sub-frame 1. 00 = Take no account of channel number (channel 1 defaults to left DAC) 01 = channel 1 to left channel 10 = channel 1 to right channel 7:6 CHNUM2[1:0] 23:22 Channel number for sub-frame 2. 00 = Take no account of channel number (channel 2 defaults to left DAC) 01 = channel 2 to left channel 10 = channel 2 to right channel Table 64 S/PDIF Receiver Channel Status Register 3 REGISTER ADDRESS BIT LABEL CHANNEL STATUS BIT DEFAULT DESCRIPTION R47 SPDRXCHAN 4 2Fh (read-only) 3:0 FREQ[3:0] 27:24 - Sampling Frequency Indicated. Refer to S/PDIF specification IEC60958-3 for details. 5:4 CLKACU[1:0] 29:28 - Clock Accuracy of received clock. 00 = Level II 01 = Level I 10 = Level III 11 = Interface frame rate not matched to sampling frequency. Table 65 S/PDIF Receiver Channel Status Register 4 REGISTER ADDRESS BIT LABEL CHANNEL STATUS BIT DEFAULT DESCRIPTION R48 SPDRXCHAN 5 30h (read-only) 0 MAXWL 32 - Maximum Audio sample word length 0 = 20 bits 1 = 24 bits 3:1 RXWL[2:0] 35:33 - Audio Sample Word Length. 000: Word Length Not Indicated RXWL[2:0] MAXWL==1 MAXWL==0 001 20 bits 16 bits 010 22 bits 18 bits 100 23 bits 19 bits 101 24 bits 20 bits 110 21 bits 17 bits All other combinations are reserved and may give erroneous operation. Data will be truncated internally when these bits are set unless WL_MASK is set. 7:4 ORGSAMP [3:0] 39:36 - Original Sampling Frequency. Refer to S/PDIF specification IEC60958-3 for details. 0000 = original sampling frequency not indicated Table 66 S/PDIF Receiver Channel Status Register 5 |
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