 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
WM8580AGEFTV Datasheet(PDF) 15 Page - Wolfson Microelectronics plc |
|
|
|||||||||||||||||||||||||||||
WM8580AGEFTV Datasheet(HTML) 15 Page - Wolfson Microelectronics plc |
|
|
15 / 106 page  Production Data WM8580A w PD, Rev 4.9, November 2013 15 CONTROL INTERFACE TIMING – 3-WIRE MODE CSB SCLK SDIN t DHO t DSU t CSH tSCY t SCS LSB SDO tDL LSB t CSS t CSU tCSM Figure 4 SPI Compatible Control Interface Input Timing Test Conditions AVDD, PVDD = 5V,DVDD = 3.3V, AGND, PGND,DGND = 0V, TA = +25 oC, fs = 48kHz, MCLK and ADCMCLK = 256fs unless otherwise stated PARAMETER SYMBOL MIN TYP MAX UNIT SCLK rising edge to CSB rising edge tSCS 60 ns SCLK pulse cycle time tSCY 80 ns SCLK duty cycle 40/60 60/40 ns SDIN to SCLK set-up time tDSU 20 ns SDIN hold time from SCLK rising edge tDHO 20 ns SDO propagation delay from SCLK falling edge tDL 5 ns CSB pulse width high tCSH 20 ns SCLK to CSB low (required for read cycle) set- up time tCSU 20 ns CSB min (write cycle only) tCSM 0.5* tSCY ns CSB rising/falling to SCLK rising tCSS 20 ns SCLK glitch suppression tps 2 8 ns Table 6 3-Wire SPI Compatible Control Interface Input Timing Information |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
