AN2388 datasheet(41/54 Pages) STMICROELECTRONICS

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AN2388

Software design

41/54

Figure 35.

Core timer T3 in incremental interface mode

Figure 36.

T3CON register configuration for incremental encoder reading

T3OUT

P3.3

T3OE

T3IR

T3OTL

Up/Down

MUX

XOR

T3UD

Phase detect

T3EUD

P3.4

T3IN

P3.6

Edge detect

T3R

Bit

Function

T3I

Timer 3 Input Selection Depends on the operating mode, see respective sections.

T3M

Timer 3 Mode Control (Basic Operating Mode)

0 0 0 : Timer Mode

0 0 1 : Counter Mode

0 1 0 : Gated Timer with Gate active low

0 1 1 : Gated Timer with Gate active high

1 0 X : Reserved. Do not use this combination

1 1 0 : Incremental Interface mode

1 1 1 : Reserved. Do not use this combination

T3R

Timer 3 Run Bit

T3R = ‘0’: Timer / Counter 3 stops

T3R = ‘1’: Timer / Counter 3 runs

T3UD

Timer 3 Up / Down Control *

T3UDE

Timer 3 External Up/Down Enable *

T3OE

Alternate Output Function Enable

T3OE = ‘0’: Alternate Output Function Disabled

T3OE = ‘1’: Alternate Output Function Enabled

T3OTL

Timer 3 Output Toggle Latch

Toggles on each overflow / underflow of T3. Can be set or reset by software.

43210

T3OTL T3OE T3UDE T3UD

T3R

T3M

T3I

T3CON (FF42h/A1h)

SFR

Reset Value: 0000h

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