Circuit description

AN3157

6/26

Doc ID 17105 Rev 1

2.2

Daughterboard circuit

This section describes the implementation of each phase network which performs the power

measurement.

The schematic can be divided into the following subsets:

●

Current sensing circuit (1) or (2)

●

Anti-aliasing filter (3)

●

Voltage sensing circuit (4)

●

Crosstalk cancellation network (5)

2.2.1

Current sensing circuit

The STPMS1 has an external current sensing circuit using either a current transformer, in

which a burden resistor is used to produce a voltage between CIN and CIP proportional to

the current measured, or a shunt resistor.

2.2.2

Anti-aliasing filter

The anti-aliasing filter is a low-pass filter which has a negligible influence on the voltage

drop between CIN and CIP, and VIN and VIP. The aim of which is to reduce the distortion

caused by the sampling (also called aliasing) by removing the out-of-band frequencies of

the input signal before sampling it with the analog-to-digital converter.

Filtering is easily implemented with a resistor-capacitor (RC) single-pole circuit which

obtains an attenuation of - 20 dB/dec.

2.2.3

Voltage sensing circuit

A resistor divider is used as a voltage sensor. The 600 k

Ω resistor is separated into four, 4 x

150 k

Ω, in-series resistors, which ensure that a high voltage transient does not bypass the

resistor. This also reduces the potential across the resistors, thereby decreasing the

possibility of arcing. The following resistors are used to implement the resistor divider:

●

R = R13 + R2 + R3 + R4 = 600 k

Ω

●

R5 = 475

Ω

The L1 inductor and the C2 capacitor create a filter which prevents electromagnetic

interference (EMI).

Figure 3.

Motherboard connector schematics

VCC

VCC

VCC

VCC

VCC

VCC

NCLK

CLK

DAR

DAS

DAT

NCLK

CLK

NCLK

CLK

J1

Card_Edge_10

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

J2

Card_Edge_10

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

J3

Card_Edge_10

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

VCC

VCC

VCC

VCC

DAN

DAH

NCLK

CLK

NCLK

CLK

J5

Card_Edge_10

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

J4

Card_Edge_10

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

VCC

VCC

VCC

VCC

VCC

VCC

NCLK

CLK

DAR

DAS

DAT

NCLK

CLK

NCLK

CLK

J1

Card_Edge_10

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

J2

Card_Edge_10

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

J3

Card_Edge_10

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

VCC

VCC

VCC

VCC

DAN

DAH

NCLK

CLK

NCLK

CLK

J5

Card_Edge_10

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

J4

Card_Edge_10

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10