Circuit description

AN3157

8/26

Doc ID 17105 Rev 1

2.2.5

Jumper settings

The on-board jumpers JP1 and JP2 allow the setting of the STPMS1 device according to

Table 2 and Table 3 below:

For further details on device configuration please refer to the device datasheet.

2.3

Clock management network

A 4.194 MHz quartz is used to supply the clock for the STPMC1 device. To set this

frequency, internal configuration bits MDIV and FR1 must be kept cleared.

A synchronized clock is provided to all STPMS1 devices through the CLK pin, the frequency

of which is programmable through bit HSA to 1.049 MHz or 2.097 MHz.

2.4

Communication with microprocessor

A control board with an embedded microprocessor may be connected to connector P1 using

a 10-wire flat cable. Table 4 describes the pinout of the connector.

The STPMC1 has an SPI communication port implemented by four multi-purpose pins

(SCS, SYN-NP, SDA-TD, SCL-NLC).

In stand-alone operating mode these multi-purpose pins produce:

●

negative power direction on the SYN-NP pin

●

tamper condition detected on the SDA-TD pin

●

no load condition detected on the SCL-NLC pin

For this reason these pins are connected to the three LEDs D9, D10 and D11.

In this configuration, the LED pin produces a pulse train with a frequency proportional to the

3-phase power and is connected to LED D12.

Table 2.

Modes of operation

JP1

MS0

Description

1

1

Rogowsky mode, ampl = 32

2

NCLK

ampl = 32 (reserved for future expansion)

3

0

Current transformer mode, ampl = 8

4

CLK

shunt mode, ampl = 32, fclk = 8*mclk

Table 3.

Changing of band-gap voltage reference

JP2

MS1

Description

1

1

TC = 190 ppm/°C

2

NCLK

TC = 125 ppm/°C

3

0

TC = 100 ppm/°C

4

CLK

TC = 170 ppm/°C