AN4121

Circuit description

Doc ID 023243 Rev 1

6/26

Figure 3.

Motherboard connectors schematics

2.2

Daughterboard circuit

This section explains the implementation of each phase network which performs the power

measurement.

The schematic can be divided into the following subsets:

●

Current sensing circuit (1) or (2)

●

Anti-aliasing filter (3)

●

Voltage sensing circuit (4).

2.2.1

Current sensing circuit

The STPMS2 has an external current sensing circuit using either a current transformer, in

which a burden resistor is used to produce a voltage between CIN and CIP proportional to

the current measured, or a shunt resistor, or a Rogowski coil current sensor.

2.2.2

Anti-aliasing filter

The anti-aliasing filter is a low-pass filter. It has a negligible influence on the voltage drop

between CIN and CIP, VIN and VIP; its aim is to reduce the distortion caused by the

sampling, also called aliasing, by removing the out-of-band frequencies of the input signal

before sampling it with the analog-to-digital converter.

Filtering is easily implemented with a resistor-capacitor (RC) single-pole circuit which

obtains an attenuation of - 20 dB/dec.

2.2.3

Voltage sensing circuit

A resistor divider is used as voltage sensor.

The 660 k

Ω resistor is separated into four, 2 x 150 kΩ and 2 x 180 kΩ, in-series resistors,

which ensure that a high voltage transient does not bypass the resistor. This also reduces

the potential across the resistors, thereby decreasing the possibility of arcing. The following

resistors are used to implement resistor divider:

●

R = R13 + R2 + R3 + R4 = 660 k

Ω

●

R5 = 470

Ω.

Inductance L1 and capacitor C2 create a filter which prevents electromagnetic interference

(EMI).

AM12745v1

VCC

VCC

VCC

VCC

VCC

VCC

NCLK

CLK

DAR

DAS

DAT

NCLK

CLK

NCLK

CLK

J1

Card_Edge_10

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

J2

Card_Edge_10

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

J3

Card_Edge_10

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

VCC

VCC

VCC

VCC

DAN

DAH

NCLK

CLK

NCLK

CLK

J5

Card_Edge_10

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

J4

Card_Edge_10

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10