AN4121

Circuit description

Doc ID 023243 Rev 1

8/26

For further details on device configuration, please refer to its datasheet.

2.3

Clock management network

A 4.194 MHz quartz is used to supply the clock to the STPMC1 device. To set this

frequency, internal configuration bits MDIV and FR1 must be kept cleared.

A synchronized clock is provided to all the STPMS2 through pin CLK, whose frequency is

programmable through bit HSA to 1.049 MHz or 2.097 MHz.

2.4

Communication with microprocessor

A control board with embedded microprocessor may be connected to connector P1 using

10-wire flat cable.

Table 5 below describes the pinout of the connector.

The STPMC1 has an SPI communication port implemented by four multipurpose pins (SCS,

SYN-NP, SDA-TD, SCL-NLC).

Table 3.

TC of the band-gap reference

JP2

MS1

Description

1

GND

TC = 60 ppm/°C

1.

Default value.

CLK

Flattest TC = +30 ppm/°C

3

NCLK

TC = +160 ppm/°C

4VDD

TC = -160 ppm/°C

Table 4.

Control of voltage channel and output signals

JP3

MS2

Description

1.

Default value.

GND

Voltage channel ON, DATn = ~(DAT =(CLK) ? bsV : bsC)

2

CLK

Voltage channel OFF, DATn = bsCn, DAT = bsC

3

NCLK

Voltage channel OFF, DATn = bsCn, DAT = bsC

4

VDD

Voltage channel ON, DATn = bsC, DAT = bsV

Table 5.

Changing of band-gap voltage reference

JP4

MS3

Description

1.

Default value.

GND

Hard mode, BIST mode OFF

2CLK

Soft mode

3

NCLK

Reserved

4VDD

Hard mode, BIST mode ON