Watchdog

AN4370

12/23

DocID025336 Rev 1

5

Watchdog

In Active Mode, as soon as the NRES pin is released, the watchdog starts with a Long Open

Window (LOW). To end the LOW and start the window watchdog, a 1 has to be written to the

WDTRIG bit in CR1 before the LOW expires (typ. 65ms). If this does not occur, a watchdog

fault event is generated; after 15 consecutive watchdog faults, the device enters VBAT

Standby Mode. Writing 0 to the WDTRIG bit during the LOW has no effect.

Once in window mode, the WDTRIG bit has to be toggled within the open window. Writing

the previous value to this bit has no effect. A watchdog trigger command is accepted only at

the CSN rising edge of the corresponding SPI frame.

When the ICMP bit is set to 1, the watchdog is disabled during VDD Standby Mode and

restarts with a LOW after a wake-up event.

Conversely, when the ICMP bit is set to 0, the watchdog state in VDD Standby Mode

depends on the current drawn from the VDD regulator (IDD). If this current is greater than

the ICMP threshold, then the watchdog remains active, otherwise it is disabled and restarts

with a LOW after a wake-up event. Moreover, if IDD becomes greater than the ICMP

threshold in VDD Standby Mode when ICMP=0, then the watchdog is automatically re-

enabled.

Watchdog failures are generated when toggling the WDTRIG bit during the closed window

or when the watchdog period or the LOW have expired.

After 8 consecutive watchdog failure events, the VDD regulator is turned off for 200ms and

then re-enabled. In case of 7 additional and consecutive watchdog failures, the device

enters VBAT Standby Mode.

When a watchdog failure occurs, the WDF bits are incremented. They are cleared as soon

as a valid watchdog trigger is received. After a watchdog failure, a reset pulse is generated

at the NRES pin, the watchdog restarts with a LOW, the FSWD flag is latched and the

device enters a fail-safe state until the FSWD flag is read and cleared via SPI.

The watchdog is always disabled in Flash Mode. To disable it in Active Mode, the WDDIS bit

has to be set to 1 in Flash Mode before entering Active Mode.