AN2335 datasheet(10/40 Pages) STMICROELECTRONICS

10 / 40 page

Digital interfaces

AN2335

10/40

4.1.1

I2C Operation

The transaction on the bus is started through a START (ST) condition which is defined as a

HIGH to LOW transition on the data line while the SCL line is held HIGH. After the START

condition has been generated by the Master, the bus is considered busy. The next byte of

data transmitted contains the address of the slave in the first 7 bits and the eighth bit tells

whether the Master is receiving data from the slave or transmitting data to the slave (SAD

subsequence). When an address is sent, each device in the system compares the first

seven bits after a start condition with its own address. If they match, the device considers

itself addressed by the Master.

The Slave ADdress (SAD) associated to the LIS302DL may be selected among the two

predefined values 0011100b or 0011101b depending on the logic level present on SDO pin.

In details, if SDO pin is either connected to Vdd_IO or left unconnected the slave address is

0011101b, otherwise when it is connected to GND the slave address is 0011100b.

Whenever it is not needed to place two sensors on the same bus it is recommended to use

the slave address 0011101b by either connecting the SDO pin to Vdd_IO or leaving it

floating.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line

during the acknowledge pulse. The receiver must then pull the data line LOW so that it

remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which

has been addressed is obliged to generate an acknowledge after each byte of data has

been received.

The I2C embedded inside the LIS302DL behaves like a slave device and the following

protocol must be adhered to. After the start condition (ST) a salve address is sent, once a

slave acknowledge (SAK) has been returned, a 8-bit sub-address will be transmitted: the 7

LSb represent the actual register address while the MSB enables address auto increment. If

the MSb of the SUB field is 1, the SUB (register address) will be automatically incremented

to allow multiple data read/write. Otherwise if the MSB of the SUB field is ‘0’, the SUB will

remain unchanged and multiple read/write on the same address can be performed.

The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated

START (SR) condition will have to be issued after the two sub-address bytes; if the bit is ‘0’

(Write) the Master will transmit to the slave with direction unchanged.

Transfer when Master is writing one byte to slave

Transfer when Master is writing multiple bytes to slave:

Transfer when Master is receiving (reading) one byte of data from slave:

Master

SAD + W

SUB

DATA

Slave

SAK

Master

SAD + W

SUB

DATA

Slave

SAK

Master

SAD + W

SUB

SAD + R

NMAK

Slave

SAK

DATA

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