AN2335 datasheet(20/40 Pages) STMICROELECTRONICS

20 / 40 page

About control registers

AN2335

20/40

Figure 10 shows the block diagram of the digital processing chain and the related control

signals.

Figure 10.

Digital Processing Chain Block Diagram

6.3

CTRL_REG3 (22h)

Control register #3.

IHL bit selects the polarity of the interrupt signal. When IHL is ‘0’ (default value) any interrupt

event will signalled with a logical 1.

PP_OD bit defines whether the interrupt pad has to work in Push-pull or in Open Drain

mode. The latter is specifically intended for wired-or connection of multiple interrupt signals

on the same interrupt line. The default value is ‘0’ which corresponds to push-pull mode.

I2CFG[2:0] and I1CFG[2:0] bit select which signal has to be sent out from the INT2 and

INT1 interrupt pads as described in the following table:

HP Filter

Interrupt Generator

(FF_WU 1)

CTRL_REG2(HP FF_WU1)

CTRL_REG3(FDS)

Regs Array

Digital Processing Chain

HP_FILTER_RESET

Interrupt Generator

(FF_WU 2)

CTRL_REG2(HP FF_WU2)

Offset

Output regs

SRC reg 1

SRC reg 2

Adjustment

Block

IHL

PP_OD

I2CFG2

I2CFG1

I2CFG0

I1CFG2

I1CFG1

I1CFG0

IHL

Interrupt active high, low. Default value 0.

(0: active high; 1: active low)

PP_OD

Push-pull/Open Drain selection on interrupt pad. Default value 0.

(0: push-pull; 1: open drain)

I2CFG2,

I2CFG0

Interrupt 2 configuration bits. Default value 000.

(see table below)

I1CFG2,

I1CFG0

Interrupt 1 configuration bits. Default value 000.

(see table below)

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