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AN2872 Datasheet(PDF) 8 Page - STMicroelectronics |
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AN2872 Datasheet(HTML) 8 Page - STMicroelectronics |
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8 / 23 page ![]() Description AN2872 8/23 Doc ID 15305 Rev 1 Figure 3. Standard implementation of a buck converter with a monolithic device The second important behavior of a buck converter dedicated for mains applications follows from the ratio between the input and output voltage. As derived from Equation 2 the duty cycle is very low when the ratio between the input and output is very high. This also means the ON time must be very short. It is possible for the ON time required for correct operation to be shorter than the minimum ON time of the controller defined in the datasheet (the maximum duration of the minimum ON time of the VIPer16 is 450 ns. see Section 6: 3). In this case the SMPS delivers more energy than the controller, which is compensated by the skipping of some pulses. This leads to higher ripple of the output voltage. This effect can be compensated by applying a higher inductance value and a lower switching frequency. The last technical point discussed in this paragraph concerns the input bulk capacitor in applications dedicated to very high input AC voltage. In this case, the input voltage is up to 500 VAC. The DC voltage can reach voltage levels of up to 707 VDC. The input bulk capacitor must be able to sustain such voltage levels. Unfortunately, there are no standard aluminum capacitors on the market suitable for this voltage, so two capacitors connected in series have been applied. The series connection of two capacitors has two effects on the voltage drop over each capacitor. The first is an influence over the tolerance of the capacitance and the second is an influence over the leakage current. Regarding the tolerance, the worst case is that one capacitor’s capacitance is at the maximum upper limit and the second at the lower limit. Equation 3 defines the voltage distribution on each capacitor for this configuration: Equation 3 where VC1 is the voltage across the capacitor with higher capacitance (the sign "–" in the brackets) VC2 is the voltage drop on the capacitor with lower capacitance (the sign "+" in the brackets) VMAX is the DC voltage bus δ is the tolerance of the capacitors expressed as a percentage If the voltage bus is 707 V and the tolerance is 20%, the highest possible voltage across the capacitor is 424 VDC. Therefore, for this voltage range, the use of 450 V capacitors is recommended. The leakage current can cause additional unbalancing of the voltages and an increase in the voltage drop of one capacitor over the allowed limit. If the leakage currents of both T1 L1 Control V1 V2 C1 C2 D1 C3 D2 FB GND AM00360 V C1 C2 , V MAX 2 -------------- 1 δ ± () = |
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