AN2476 datasheet(14/49 Pages) STMICROELECTRONICS

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Power supply and clocks

AN2476

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1.8

Low power modes

Several low power modes are implemented to reach the best compromise between lowest

power consumption, fastest start-up time and available wake-up sources:

●

SLOW MODE: System clock speed is reduced

●

PCG MODE: APB Peripherals Clock Gating

●

WFI MODE: Wait For Interrupts

●

STOP MODE: All clocks are disabled

●

STANDBY MODE: Part of the chip is unpowered

Software has to execute the low power bit writing sequence (see below) to enter WFI, STOP

or STANDBY modes. This sequence protects the application from entering a low power

mode unintentionally.

1.8.1

Low power bit writing sequence

WFI, STOP or STANDBY modes are entered by software writing the following specific

sequence to the LP bit in the MRCC_PWRCTRL register.

Before executing the sequence, LP_DONE bit status must be previously cleared.

●

Write LP bit to ‘1’

●

Write LP bit to ‘1’

●

Write LP bit to ‘0’

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Write LP bit to ‘1’

●

Read LP: if successful, LP is first read at 1 and then cleared by hardware when

entering in Low Power Mode.

This sequence is performed by internal function of the library Section 2: STR750 library low

power mode functions on page 26.

If this sequence is not performed correctly or if LP_DONE was not cleared, the sequence is

automatically reset and must be re-executed from the beginning.

To abort the sequence, simply write twice the LP bit to ‘0’.

The LP_DONE status flag is set after a successful LP bit writing sequence (meaning that

the system has entered and exited the low power mode). This information is useful to know

if the low power mode has been effectively entered or not.

As soon as the LP bit writing sequence is initiated:

●

The MRCC_PWRCTRL register is locked (any write access other than to the LP bit will

be discarded) until the sequence is completed or aborted

●

Interrupts are masked (IRQ and FIQ signals to the ARM CPU are gated) until the

sequence is completed or aborted

Any interrupts which occur during this sequence will not be lost: they will be served after the

sequence is completed or aborted.

Before performing the sequence, all pending bit interrupts used to wake-up from STOP

mode should be cleared.

If any interrupts from an external interrupt line, an RTC alarm or NCKDF (no clock detected)

event are still pending, the sequence will not performed correctly.

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