AN2710

STR7x atomic bit set or bit reset (bit-wise write operations)

19/30

3

STR7x atomic bit set or bit reset (bit-wise write

operations)

The bitwise instructions proposed by the "ARM7 Instruction Set" only apply to the internal

ARM7 Ri registers. Consequently, it is not possible to directly perform bitwise write

operations (like a bit set or a bit clear) on an I/O Port register. Three operations are required:

●

Load the whole Port Data register into an Ri register

●

Modify the Ri register using the bitwise ARM7 instruction

●

Store back the whole result from the Ri register into the Port Data Register

Since this is not an atomic operation, an interrupt subroutine (ISR) may happen to be served

between the load access and the store access. If the ISR sets or clears some other Port

register bits, the port might be corrupted when the data are stored back into the Port

register. Consequently, if the interrupt subroutines are susceptible to modify the other bits of

the I/O port being written, it is recommended to disable the interrupts during bitwise write

operations.

With the STR75x, however, this is not needed because it features a Port Mask Register. The

purpose of the Port Mask Register is to allow atomic read/modify accesses (or bitwise write

operations) to any of the GPIO registers. In this case, you simply need to:

●

first program the Port Mask Register (PxM) to mask the bits that you do not want

modified

●

then, program the port registers (PxC2, PxC1, PxC0 and PxD). The masked bits will

not be modified.

This mask applies to all the Configuration and Data registers (PxC3, PxC1, PxC0 and PxD).

Note:

It is recommended that each interrupt subroutine that accesses the port registers stacks the

Port Mask Register. Otherwise, an interrupt occurring between the modification of the PxM

register and a bit manipulation on the PxD registers might lead to a corruption of the port

bits.