Clocks

AN4325

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DocID024966 Rev 1

2.6

Clock security system (CSS)

The clock security system can be activated by software. In this case, the clock detector is

enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.



If a failure is detected on the HSE oscillator clock, the oscillator is automatically

disabled.

–

A clock failure event is sent to the break inputs of TIM1 advanced control timer

and TIM15, TIM16 and TIM17 general purpose timers.

–

An interrupt is generated to inform the software about the failure (clock security

system interrupt CSSI), allowing the MCU to perform recovery operations.

–



If the HSE oscillator is used directly or indirectly as the system clock (indirectly means

that it is used as the PLL input clock, and the PLL clock is used as the system clock), a

detected failure causes a switch of the system clock to the HSI oscillator and the

disabling of the external HSE oscillator. If the HSE oscillator clock (divided or not) is the

clock entry of the PLL that is being used as a system clock when the failure occurs, the

PLL is disabled too.

For details, see the RM0360 reference manual available from the STMicroelectronics

website www.st.com.