UM1653 datasheet(8/45 Pages) STMICROELECTRONICS

8 / 45 page

STM32 NAND driver blocks

UM1653

8/45

DocID025024 Rev 1

Bulk-Only Transport State machine

#define BOT_IDLE

//Idle state

#define BOT_DATA_OUT

//Data Out state

#define BOT_DATA_IN

//Data In state

#define BOT_DATA_IN_LAST

//Last Data In Last

#define BOT_CSW_Send

//Command Status Wrapper

#define BOT_ERROR

//error state

#define BOT_CBW_SIGNATURE

0x43425355

//1st 4 bytes of CBW pkt

#define BOT_CSW_SIGNATURE

0x53425355

//1st 4 bytes of CSW pkt

#define BOT_CBW_PACKET_LENGTH

#define CSW_DATA_LENGTH

CSW Status Definitions

#define CSW_CMD_PASSED

0x00

#define CSW_CMD_FAILED

0x01

#define CSW_PHASE_ERROR

0x02

#define SEND_CSW_DISABLE

#define SEND_CSW_ENABLE

#define DIR_IN

#define DIR_OUT

#define BOTH_DIR

1.3

FSMC

The FSMC block is able to communicate with the synchronous and asynchronous memory.

Its main purpose is to:



Translate the AHB protocol transactions of external devices



Respect the access time of external devices

The FSMC provides a single access to an external device.

The FSMC has four blocks:



AHB Interface



Controller NOR Flash / PSRAM



Controller NAND Flash / PC Card



Interface to external device

The FSMC generates the appropriate signals to drive the NAND Flash memory.

The FSMC controller consists of two blocks of code error correction hardware. They reduce

the workload on the host processor when processing code error correction by the system

software. These two blocks are identical and are respectively associated with banks 2 and

3. The ECC algorithm used in the FSMC can perform 1- and 2-bit error detection.

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