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AN4660 Datasheet(PDF) 19 Page - STMicroelectronics |
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AN4660 Datasheet(HTML) 19 Page - STMicroelectronics |
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19 / 27 page ![]() DocID027558 Rev 2 19/27 AN4660 Peripheral migration 26 2.11 U(S)ART The U(S)ART is not SW compatible with STM32F42xxx/F43xxx and includes new additional features detailed in Table 16. Table 16. U(S)ART differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx U(S)ART STM32F42xxx/F43xxx STM32F74xxx/F75xxx UART/USART 4/4 Baud rate – Up to 4x11.25 Mbit/s – Up to 13.5 Mbit/s – (clock frequency is 100 MHz and oversampling is by 8) Clock – Single clock domain – Dual clock domain: Convenient baud rate programming independent from the PCLK reprogramming Data – Word length: Programmable (8 or 9 bits) – Word length: Programmable (7, 8 or 9 bits) – Programmable data order with MSB- first or LSB-first shifting interrupt – 10 interrupt sources with flags – 14 interrupt sources with flags Features – LIN mode – SPI Master – IrDA SIR ENDEC block – Hardware flow control (CTS/RTS) – Continuous communication using DMA – Multiprocessor communication – Single-wire half-duplex communication Smartcard mode T = 0 and T= 1 has to be implemented by software. Number of stop bits: 0.5, 1, 1.5, 2 Support the T=0 and T=1 asynchronous protocols. Number of stop bits: 1, 1.5, 2 smartcard operation. NA – Support for ModBus communication - Timeout feature - CR/LF character recognition – Receiver timeout interrupt – Auto baud rate detection – Driver Enable – Swappable Tx/Rx pin configuration U(S)ART registers – Software not compatible |
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