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UPD72001C Datasheet(PDF) 17 Page - NEC |
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UPD72001C Datasheet(HTML) 17 Page - NEC |
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17 / 40 page  µPD72001-11, 72001-A8 17 Serial control: Parameter Symbol Condition Rated Value Unit MIN. MAX. Transmit/receive data cycle tCYD 5tCYK STRXC, TRXC input clock cycle tCYC 90 ns STRXC, TRXC input High tWCH 40 ns clock pulse width Low tWCL TA = –10 to +70 °C40 ns TA = –40 to +85 °C45 STRXC, TRXC ↓ → TXD delay time tDTCTD1 ×1 mode, COP, BOP 100 ns tDTCTD2 ×16, 32, 64 mode 300 ns TRXC ↓ → TXD delay time tDTCTD3 TRXC is output 0 100 ns RXD setup time (vs. STRXC, TRXC ↑)tSRDRC When DPLL is not used 0 ns RXD hold time (vs. STRXC, TRXC ↑)tHRCRD When DPLL is not used 120 ns RXD → TXD delay time tDRDTD1 ECHO BACK mode 100 ns tDRDTD2 Without SDLC Loop delay 100 ns TXD → INT delay time tDTDIQ TX INT mode 4 6 tCYK TXD → DRQTX delay time tDTDDQ TX DMA mode 4 6 tCYK RXC ↑ Note → INT delay time tDRCIQ RX INT mode 7 11 tCYK RXC ↑ Note → DRQRX delay time tDRCDQ RX DMA mode 7 11 tCYK RD ↓ → DRQRX ↓ delay time tDRDQ 120 ns WR ↓ → DRQTX ↓ delay time tDWDQ 120 ns Note Of STRXC and TRXC, the one used as the receive clock. Interrupt control: Parameter Symbol Condition Rated Value Unit MIN. MAX. INTAK low-pulse width tWIAL 120 ns INTAK high-pulse width tWIAH 120 ns PRI → PRO delay time tDPIPO 50 ns INT ↓ → PRO ↑ delay time tDIQPO –20 +50 ns 2nd INTAK ↓ → INT ↑ delay time tDIAIQ INT output level = 0.8 VNote 120 ns INT output level = 2.2 VNote 300 ns SR2B read RD ↓ → INT ↑delay time tDRDIQ INT output level = 0.8 VNote 150 ns INT output level = 2.2 VNote 300 ns PRI setup time (vs. INTAK ↓)tSPIIA1 When vector output is enabled 0 ns PRI hold time (vs. INTAK ↑)tHIAPI1 20 ns PRI setup time (vs. INTAK ↓)tSPIIA2 When vector output is disabled 20 ns PRI hold time (vs. INTAK ↑)tHIAPI2 20 ns INTAK → data output delay time tDIAD 120 ns INTAK → data float delay time tFIAD 10 85 ns Note Measured value with 2-k Ω pull-up resistor and 100-pF load capacitance connected |
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