STC5455 datasheet(43/56 Pages) CONNOR-WINFIELD

43 / 56 page

Page 43 of 56 TM121

Rev:P1.3

Date: October 24, 2011

STC5455

Synchronous Clock for SETS

Data sheet

Preliminary

Phase skew adjust for synthesizer G1, G2, or F based on the selection at the register Synth_Index_Select.

Synthesizer GT4 is not phase skew programmable. The adjustment is from -6400/128 ns to 6396.875/128

ns, which is -50ns ~ 49.976 ns, in 3.125/128 ns steps, 2’s complement.

Default value: 0 (For all the synthesizers)

CLK1_Signal_Level, 0x50 (R/W)

Selects the signal level for clock outputs CLK1

0 = LVPECL, 1 = LVDS

Default value: 0

CLK1_Sel, 0x51(R/W)

Selects clock output CLK1 derived from synthesizer G1 or put in tri-state.

Default value: 0

CLK2_Sel, 0x52 (R/W)

Selects the clock output CLK2 derived from synthesizer G2 (T0) or synthesizer GT4(T4). Frame8K and

Frame2K are produced at synthesizer F. When synthesizer F is selected, sets bit1~bit0 of the register

Frame_Mux to select frame pulse clock Frame8K or Frame2K. Signal level of CLK2 is LVCMOS.

Synthesizer Index Selection

Associated CLK Output

Synthesizer F

CLK8K, CLK2K, CLK2

Synthesizer G1

CLK1

Synthesizer G2

CLK2

Address

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0x50

Not used

CLK1 Signal Level

Address

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0x51

Not used

CLK1 Synthesizer Select

Bits 1 ~ 0

CLK1 Synthesizer Select

0, 2, 3

Put CLK1 in tri-state mode

Synthesizer G1

Address

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0x52

Not used

CLK2 Synthesizer Select

Frame_Mux

(Bit1~Bit0)

Bits 1 ~ 0

CLK2 Synthesizer Select

Put CLK2 in tri-state mode

STC5455 Datasheet(PDF) 43 Page - Connor-Winfield Corporation

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