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NX3L1G53 Datasheet(PDF) 3 Page - NXP Semiconductors |
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NX3L1G53 Datasheet(HTML) 3 Page - NXP Semiconductors |
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3 / 24 page ![]() NX3L1G53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 7 — 8 February 2013 3 of 24 NXP Semiconductors NX3L1G53 Low-ohmic single-pole double-throw analog switch 7. Pinning information 7.1 Pinning Fig 2. Logic diagram 001aad387 Z Y0 S Y1 E Fig 3. Pin configuration SOT833-1 (XSON8) Fig 4. Pin configuration SOT996-2 (XSON8) NX3L1G53 Y1 Y0 VCC S GND E Z GND 001aah454 36 27 18 45 Transparent top view 001aaj534 NX3L1G53 Transparent top view 8 7 6 5 1 2 3 4 Z E GND GND VCC Y0 Y1 S |
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