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TLS820F0

Block Description and Electrical Characteristics

Data Sheet

Rev. 1.1, 2015-07-27

Watchdog deactivation by external signal (pin “WI”)

Note: Disabling the watchdog should only considered when the application is not running in the normal operating

conditions as the safe operation is not ensured any more. Example would be the flashing process of the

microcontroller.

The Watchdog can be disabled by connecting a voltage level between the range of 1.15 V to 1.40 V to WI. By

entering the Watchdog deactivation, the “WO” signal behaves like it is described in Figure 12. The transition from

active to an inactive state will be performed after a dead time of

WI,filter,max, when correct level to WI pin is applied.

This protects against the unintended entering of watchdog deactivation state. After leaving the deactivation

voltage range 1.15 V to 1.40 V, the Watchdog is again active and starts with an ignore window. This scenario is

also valid for the transition from deactivation to activation state.

Figure 12

Watchdog Output behavior for Watchdog deactivation by WI pin

Scenario “A”

In scenario “A” the watchdog logic expects a next trigger at WI pin within the WD-trigger time

WI,tr. This state is

interrupted by setting

WI to the disable condition (VWI,dis,low ≤ VWI ≤ VWI,dis,high). During this state, the watchdog is

disabled. The watchdog output signal “WO” will stay high while the watchdog is disabled. After leaving the disable

condition (

WI ≥ VWI,dis,high or VWI ≤ VWI,dis,low), an ignore window tWI,i follows. After this, the watchdog trigger time

WI,tr starts based on the setting of the DT pins. This behavior is defined for cases with a low current load time

greater than

WO,low.

Scenario “B”

In scenario “B” the watchdog is not served within WD-trigger time

WI,tr with an trigger event at WI pin. As a result

the “WO” is set to low. This state is interrupted by setting

WI to the disable condition (VWI,dis,low ≤ VWI ≤ VWI,dis,high).

During this state, the watchdog is disabled. The watchdog output signal “WO” is kept in low state for

WO,low and

then the “WO” is set to high. After leaving the disable condition (

WI ≥ VWI,dis,high or VWI ≤ VWI,dis,low), an ignore

window

WI,i follows. After this, the watchdog trigger time tWI,tr starts based on the setting of the DT pins. This

behavior is defined for cases with a low current load time greater than

WO,low.

Scenario “C”

In scenario “C” the watchdog is not served within WD-trigger time

WI,tr with an trigger event at WI pin. As a result

the “WO” is set to low. After this an ignore window follows. This state is interrupted by setting

WI to the disable

condition (

WI,dis,low ≤ VWI ≤ VWI,dis,high). During this state, the watchdog is disabled. The watchdog output signal

“WO” will stay high while the watchdog is disabled. After leaving the disable condition (

WI ≥ VWI,dis,high or

VWI

VWI,dis.high

VWI,dis,low

VWO

>tWO,low

Scenario „A“

WD-trigger time tWI,tr *)

WD disabled

ignore time tWI,i

WD-trigger time tWI,tr

VWO

Scenario „B“

WD-trigger time tWI,tr

ignore time tWI,i

WD-trigger time tWI,tr

tWO,low

VWO

Scenario „C“

WD-trigger time tWI,tr

ignore time tWI,i

WD-trigger time tWI,tr

tWO,low

WD disabled

VWO

Scenario „D“

WD-trigger time tWI,tr

ignore time tWI,i

WD-trigger time tWI,tr

tWO,low

WD disabled

*) interrupted by entering in „Watchdog deactivation by WI pin“

Watchdog filter time tW,IQ,filter

VWI

VWI,dis.high

VWI,dis,low

<tWO,low

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