PIC16CE623-04SLASHSS datasheet(30/108 Pages) MICROCHIP

30 / 108 page

PIC16CE62X

DS40182A-page 30

Preliminary

6.1

BUS CHARACTERISTICS

In this section, the term “processor” refers to the portion

of the PIC16CE62X that interfaces to the EEPROM

through software manipulating the EEINTF register.

The following bus protocol is to be used with the

EEPROM data memory.

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted by the EEPROM as a START or STOP

condition.

Accordingly, the following bus conditions have been

deﬁned (Figure 6-2).

6.1.1

BUS NOT BUSY (A)

Both data and clock lines remain HIGH.

6.1.2

START DATA TRANSFER (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition. All

commands must be preceded by a START condition.

6.1.3

STOP DATA TRANSFER (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

6.1.4

DATA VALID (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one bit of data per

clock pulse.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the processor and

is theoretically unlimited, although only the last sixteen

will be stored when doing a write operation. When an

overwrite does occur, it will replace data in a ﬁrst-in,

ﬁrst-out fashion.

6.1.5

ACKNOWLEDGE

The EEPROM will generate an acknowledge after the

reception of each byte. The processor must generate

an extra clock pulse which is associated with this

acknowledge bit.

When the EEPROM acknowledges, it pulls down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse.

course, setup and hold times must be taken into

account. The processor must signal an end of data to

the EEPROM by not generating an acknowledge bit on

the last byte that has been clocked out of the EEPROM.

In this case, the EEPROM must leave the data line

HIGH to enable the processor to generate the STOP

condition (Figure 6-3).

Note:

Acknowledge bits are not generated if an

internal programming cycle is in progress.

62X.bk Page 30 Tuesday, March 10, 1998 3:40 PM

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