PIC16CE623-04SLASHSS datasheet(53/108 Pages) MICROCHIP

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Preliminary

DS40182A-page 53

PIC16CE62X

10.3

Reset

The PIC16CE62X differentiates between various kinds

of reset:

Power-on reset (POR)

MCLR reset during normal operation

MCLR reset during SLEEP

WDT reset (normal operation)

WDT wake-up (SLEEP)

Brown-out Reset (BOR)

Some registers are not affected in any reset condition;

their status is unknown on POR and unchanged in any

other reset. Most other registers are reset to a “reset

state” on Power-on reset, on MCLR or WDT reset and

on MCLR reset during SLEEP. They are not affected by

a WDT wake-up, since this is viewed as the resumption

of normal operation. TO and PD bits are set or cleared

differently in different reset situations as indicated in

Table 10-4. These bits are used in software to deter-

mine the nature of the reset. See Table 10-6 for a full

description of reset states of all registers.

A simpliﬁed block diagram of the on-chip reset circuit is

shown in Figure 10-7.

The MCLR reset path has a noise ﬁlter to detect and

ignore small pulses. See Table 13-6 for pulse width

speciﬁcation.

FIGURE 10-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR/

VDD

OSC1/

WDT

Module

VDD rise

detect

OST/PWRT

On-chip(1)

RC OSC

WDT

Time-out

Power-on Reset

OST

PWRT

Chip_Reset

10-bit Ripple-counter

Reset

Enable OST

Enable PWRT

SLEEP

See Table 10-3 for time-out situations.

Note 1:

This is a separate oscillator from the RC oscillator of the CLKIN pin.

Brown-out

Reset

BODEN

CLKIN

VPP Pin

10-bit Ripple-counter

62X.bk Page 53 Tuesday, March 10, 1998 3:40 PM

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