PIC16CE623-04SLASHSS datasheet(32/108 Pages) MICROCHIP

32 / 108 page

PIC16CE62X

DS40182A-page 32

Preliminary

6.3

WRITE OPERATIONS

6.3.1

BYTE WRITE

Following the start signal from the processor, the

device code (4 bits), the don't care bits (3 bits), and the

R/W bit which is a logic low is placed onto the bus by

the processor. This indicates to the EEPROM that a

byte with a word address will follow after it has gener-

ated an acknowledge bit during the ninth clock cycle.

Therefore the next byte transmitted by the processor is

the word address and will be written into the address

pointer of the EEPROM.

After receiving another

acknowledge signal from the EEPROM the processor

will transmit the data word to be written into the

addressed memory location. The EEPROM acknowl-

edges again and the processor generates a stop con-

dition. This initiates the internal write cycle, and during

this time the EEPROM will not generate acknowledge

signals (Figure 6-6).

6.3.2

PAGE WRITE

The write control byte, word address and the ﬁrst data

byte are transmitted to the EEPROM in the same way

as in a byte write. But instead of generating a stop con-

dition the processor transmits up to eight data bytes to

the EEPROM which are temporarily stored in the on-

chip page buffer and will be written into the memory

after the processor has transmitted a stop condition.

After the receipt of each word, the three lower order

address pointer bits are internally incremented by one.

The higher order ﬁve bits of the word address remains

constant. If the processor should transmit more than

eight words prior to generating the stop condition, the

address counter will roll over and the previously

received data will be overwritten. As with the byte write

operation, once the stop condition is received an inter-

nal write cycle will begin (Figure 6-7).

6.4

ACKNOWLEDGE POLLING

Since the EEPROM will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write com-

mand has been issued from the processor, the

EEPROM initiates the internally timed write cycle. ACK

polling can be initiated immediately. This involves the

processor sending a start condition followed by the

control byte for a write command (R/W = 0). If the

device is still busy with the write cycle, then no ACK will

be returned. If no ACK is returned, then the start bit and

control byte must be re-sent. If the cycle is complete,

then the device will return the ACK and the processor

can then proceed with the next read or write command.

See Figure 6-5 for ﬂow diagram.

FIGURE 6-5:

ACKNOWLEDGE POLLING

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did EEPROM

Acknowledge

(ACK = 0)?

Operation

YES

FIGURE 6-6:

BYTE WRITE

BUS ACTIVITY

PROCESSOR

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

WORD

ADDRESS

DATA

X = Don’t Care Bit

62X.bk Page 32 Tuesday, March 10, 1998 3:40 PM

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