PIC16CE623-04SLASHSS datasheet(18/108 Pages) MICROCHIP

18 / 108 page

PIC16CE62X

DS40182A-page 18

Preliminary

4.2.2.4

PIE1 REGISTER

This register contains the individual enable bit for the

comparator interrupt.

FIGURE 4-9:

PIE1 REGISTER (ADDRESS 8CH)

U-0

R/W-0

U-0

—

CMIE

—

= Readable bit

W = Writable bit

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7:

Unimplemented: Read as '0'

bit 6:

CMIE: Comparator Interrupt Enable bit

1 = Enables the Comparator interrupt

0 = Disables the Comparator interrupt

bit 5-0: Unimplemented: Read as '0'

4.2.2.5

PIR1 REGISTER

This register contains the individual ﬂag bit for the com-

parator interrupt.

Note:

Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable

bit,

GIE

(INTCON<7>).

User

software should ensure the appropriate

interrupt ﬂag bits are clear prior to enabling

an interrupt.

FIGURE 4-10: PIR1 REGISTER (ADDRESS 0CH)

U-0

R/W-0

U-0

—

CMIF

—

= Readable bit

W = Writable bit

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7:

Unimplemented: Read as '0'

bit 6:

CMIF: Comparator Interrupt Flag bit

1 = Comparator input has changed

0 = Comparator input has not changed

bit 5-0: Unimplemented: Read as '0'

62X.bk Page 18 Tuesday, March 10, 1998 3:40 PM

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