PIC16CE623-04SLASHSS datasheet(33/108 Pages) MICROCHIP

33 / 108 page

Preliminary

DS40182A-page 33

PIC16CE62X

FIGURE 6-7:

PAGE WRITE

BUS ACTIVITY

PROCESSOR

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n

DATAn + 7

DATAn + 1

6.5

READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

EEPROM address is set to one. There are three basic

types of read operations: current address read, random

read, and sequential read.

6.6

Current Address Read

The EEPROM contains an address counter that main-

tains the address of the last word accessed, internally

incremented by one. Therefore, if the previous access

(either a read or write operation) was to address n, the

next current address read operation would access data

from address n + 1. Upon receipt of the EEPROM

address with R/W bit set to one, the EEPROM issues

an acknowledge and transmits the eight bit data word.

The processor will not acknowledge the transfer but

does generate a stop condition and the EEPROM dis-

continues transmission (Figure 6-8).

6.7

Random Read

Random read operations allow the processor to access

any memory location in a random manner. To perform

this type of read operation, ﬁrst the word address must

be set. This is done by sending the word address to the

EEPROM as part of a write operation. After the word

address is sent, the processor generates a start condi-

tion following the acknowledge. This terminates the

write operation, but not before the internal address

pointer is set. Then the processor issues the control

byte again but with the R/W bit set to a one. The

EEPROM will then issue an acknowledge and trans-

mits the eight bit data word. The processor will not

acknowledge the transfer but does generate a stop

condition and the EEPROM discontinues transmission

(Figure 6-9).

6.8

Sequential Read

Sequential reads are initiated in the same way as a ran-

dom read except that after the EEPROM transmits the

ﬁrst data byte, the processor issues an acknowledge as

opposed to a stop condition in a random read. This

directs the EEPROM to transmit the next sequentially

addressed 8-bit word (Figure 6-10).

To provide sequential reads the EEPROM contains an

internal address pointer which is incremented by one at

the completion of each operation. This address pointer

allows the entire memory contents to be serially read

during one operation.

6.9

Noise Protection

The EEPROM employs a VCC threshold detector circuit

which disables the internal erase/write logic if the VCC

is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and ﬁlter

circuits which suppress noise spikes to assure proper

device operation even on a noisy bus.

62X.bk Page 33 Tuesday, March 10, 1998 3:40 PM

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