PIC16C641-04SLASHSP datasheet(32/136 Pages) MICROCHIP

32 / 136 page

PIC16C64X & PIC16C66X

DS30559A-page 32

Preliminary

5.2

PORTB and TRISB Registers

PORTB is an 8-bit wide bi-directional port. The

corresponding data direction register is TRISB. Setting

a bit in the TRISB register puts the corresponding out-

put driver in a hi-impedance mode. Clearing a bit in the

TRISB register puts the contents of the output latch on

the selected pin(s).

Reading PORTB register reads the status of the pins,

whereas writing to it will write to the port latch. All write

operations are read-modify-write operations. There-

fore, a write to a port implies that the port pins are read,

this value is modiﬁed, and then written to the port data

latch.

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is

done by clearing the RBPU (OPTION<7>) bit. The

weak pull-up is automatically turned off when the port

pin is conﬁgured as an output. The pull-ups are dis-

abled on a Power-on Reset.

Four of PORTB’s pins, RB7:RB4, have an interrupt on

change feature. Only pins conﬁgured as inputs can

cause this interrupt to occur (i.e., any RB7:RB4 pin

conﬁgured as an output is excluded from the interrupt

on change comparison). The input pins (of RB7:RB4)

are compared with the old value latched on the last

read of PORTB. The “mismatch” outputs of RB7:RB4

are OR’ed together to generate the RBIF interrupt (ﬂag

latched in (INTCON<0>)).

FIGURE 5-5:

BLOCK DIAGRAM OF

RB7:RB4 PINS

Data Latch

From other

RBPU(2)

VDD

I/O

Data bus

WR Port

WR TRIS

Set RBIF

TRIS Latch

RD TRIS

RD Port

RB7:RB4 pins

weak

pull-up

RD Port

Latch

TTL

Input

Buffer

pin(1)

Note 1: I/O pins have diode protection to VDD and VSS.

2: TRISB = '1' enables weak pull-up if RBPU = '0'

(OPTION<7>).

Buffer

RB7:RB6 in serial programming mode

This interrupt can wake the device from SLEEP. The

user, in the interrupt service routine, can clear the

interrupt in the following manner:

Any read or write of PORTB. This will end the

mismatch condition.

Clear ﬂag bit RBIF.

A mismatch condition will continue to set ﬂag bit RBIF.

Reading PORTB will end the mismatch condition, and

allow ﬂag bit RBIF to be cleared.

This interrupt on mismatch feature, together with

software conﬁgurable pull-ups on these four pins allow

easy interface to a keypad and make it possible for

wake-up on key-depression. (See AN552 in the

Microchip

Embedded Control Handbook.)

The interrupt on change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt on change

feature. Polling of PORTB is not recommended while

using the interrupt on change feature.

FIGURE 5-6:

BLOCK DIAGRAM OF

RB3:RB0 PINS

Data Latch

RBPU(2)

VDD

Data bus

WR Port

WR TRIS

RD TRIS

RD Port

weak

pull-up

RD Port

RB0/INT

I/O

pin(1)

TTL

Input

Buffer

Note 1: I/O pins have diode protection to VDD and VSS.

2: TRISB = '1' enables weak pull-up if RBPU = '0'

(OPTION<7>).

Buffer

PIC16C641-04/SP Datasheet(PDF) 32 Page - Microchip Technology

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